cvt_V1724.c

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// File includes
#include <memory.h>
#include <string.h>
#include "cvt_V1724.h"

//
// CAENVMELib function prototype
void delay( int msec);

// File local defines

// Output buffer macros

// Output buffer macros
#define V1724_DATA_TYPE_MSK                             0xf8000000              
#define V1724_GLOBAL_HEADER                             0x40000000              
#define V1724_GLOBAL_TRAILER                    0x80000000              
#define V1724_TDC_HEADER                                0x08000000              
#define V1724_TDC_MEASURE                               0x00000000              
#define V1724_TDC_ERROR                                 0x20000000              
#define V1724_TDC_TRAILER                               0x18000000              
#define V1724_GLOBAL_TRIGGER_TIME               0x88000000              
#define V1724_FILLER                                    0xc0000000              
#define IS_GLOBAL_HEADER(data)                  ((data& V1724_DATA_TYPE_MSK)== V1724_GLOBAL_HEADER)                     
#define IS_GLOBAL_TRAILER(data)                 ((data& V1724_DATA_TYPE_MSK)== V1724_GLOBAL_TRAILER)            
#define IS_TDC_HEADER(data)                             ((data& V1724_DATA_TYPE_MSK)== V1724_TDC_HEADER)                        
#define IS_TDC_MEASURE(data)                    ((data& V1724_DATA_TYPE_MSK)== V1724_TDC_MEASURE)                       
#define IS_TDC_ERROR(data)                              ((data& V1724_DATA_TYPE_MSK)== V1724_TDC_ERROR)                         
#define IS_TDC_TRAILER(data)                    ((data& V1724_DATA_TYPE_MSK)== V1724_TDC_TRAILER)                       
#define IS_GLOBAL_TRIGGER_TIME(data)    ((data& V1724_DATA_TYPE_MSK)== V1724_GLOBAL_TRIGGER_TIME)       
#define IS_FILLER(data)                                 ((data& V1724_DATA_TYPE_MSK)== V1724_FILLER)                            
#define GET_EVENT_COUNT(data)                   ((UINT32)((((UINT32)data)>>5)& 0x003fffff))                                     

// Static variables declaration




static const cvt_reg_table CVT_V1724_REG_TABLE[]=
{
//
// Channel broadcast registers
        {CVT_V1724_BROAD_CH_CTRL_ADD,                   CVT_V1724_BROAD_CH_CTRL_AM,                     CVT_V1724_BROAD_CH_CTRL_DATA_SIZE},                             
        {CVT_V1724_BROAD_CH_SET_CTRL_ADD,               CVT_V1724_BROAD_CH_SET_CTRL_AM,         CVT_V1724_BROAD_CH_SET_CTRL_DATA_SIZE},                 
        {CVT_V1724_BROAD_CH_CLEAR_CTRL_ADD,             CVT_V1724_BROAD_CH_CLEAR_CTRL_AM,       CVT_V1724_BROAD_CH_CLEAR_CTRL_DATA_SIZE},               
        {CVT_V1724_BROAD_CH_BLKSIZE_ADD,                CVT_V1724_BROAD_CH_BLKSIZE_AM,          CVT_V1724_BROAD_CH_BLKSIZE_DATA_SIZE},                  
        {CVT_V1724_BROAD_CH_BLK_REM_NUM_ADD,    CVT_V1724_BROAD_CH_BLK_REM_NUM_AM,      CVT_V1724_BROAD_CH_BLK_REM_NUM_DATA_SIZE},              
        {CVT_V1724_BROAD_CH_READ_CONF_ADD,              CVT_V1724_BROAD_CH_READ_CONF_AM,        CVT_V1724_BROAD_CH_READ_CONF_DATA_SIZE},                
//
// VME registers
        {CVT_V1724_CONTROL_ADD,                                 CVT_V1724_CONTROL_AM,                           CVT_V1724_CONTROL_DATA_SIZE},                                   
        {CVT_V1724_STATUS_ADD,                                  CVT_V1724_STATUS_AM,                            CVT_V1724_STATUS_DATA_SIZE},                                    
        {CVT_V1724_INT_LEVEL_ADD,                               CVT_V1724_INT_LEVEL_AM,                         CVT_V1724_INT_LEVEL_DATA_SIZE},                                 
        {CVT_V1724_INT_VECTOR_ADD,                              CVT_V1724_INT_VECTOR_AM,                        CVT_V1724_INT_VECTOR_DATA_SIZE},                                
        {CVT_V1724_GEO_ADDRESS_ADD,                             CVT_V1724_GEO_ADDRESS_AM,                       CVT_V1724_GEO_ADDRESS_DATA_SIZE},                               
        {CVT_V1724_MCST_CBLT_ADDRESS_ADD,               CVT_V1724_MCST_CBLT_ADDRESS_AM,         CVT_V1724_MCST_CBLT_ADDRESS_DATA_SIZE},                 
        {CVT_V1724_MCST_CBLT_CTRL_ADD,                  CVT_V1724_MCST_CBLT_CTRL_AM,            CVT_V1724_MCST_CBLT_CTRL_DATA_SIZE},                    
        {CVT_V1724_SW_RESET_ADD,                                CVT_V1724_SW_RESET_AM,                          CVT_V1724_SW_RESET_DATA_SIZE},                                  
        {CVT_V1724_SW_CLEAR_ADD,                                CVT_V1724_SW_CLEAR_AM,                          CVT_V1724_SW_CLEAR_DATA_SIZE},                                  
        {CVT_V1724_SW_TRIGGER_ADD,                              CVT_V1724_SW_TRIGGER_AM,                        CVT_V1724_SW_TRIGGER_DATA_SIZE},                                
        {CVT_V1724_TRIGGER_ENABLE_ADD,                  CVT_V1724_TRIGGER_ENABLE_AM,            CVT_V1724_TRIGGER_ENABLE_DATA_SIZE},                    
        {CVT_V1724_BLT_EVENT_NUM_ADD,                   CVT_V1724_BLT_EVENT_NUM_AM,                     CVT_V1724_BLT_EVENT_NUM_DATA_SIZE},                             
        {CVT_V1724_FW_REV_ADD,                                  CVT_V1724_FW_REV_AM,                            CVT_V1724_FW_REV_DATA_SIZE},                                    
        {CVT_V1724_TEST_REG_ADD,                                CVT_V1724_TEST_REG_AM,                          CVT_V1724_TEST_REG_DATA_SIZE},                                  
        {CVT_V1724_FLASH_EN_ADD,                                CVT_V1724_FLASH_EN_AM,                          CVT_V1724_FLASH_EN_DATA_SIZE},                                  
        {CVT_V1724_FLASH_ADD,                                   CVT_V1724_FLASH_AM,                                     CVT_V1724_FLASH_DATA_SIZE},                                             
        {CVT_V1724_DUMMY16_ADD,                                 CVT_V1724_DUMMY16_AM,                           CVT_V1724_DUMMY16_DATA_SIZE},                                   
        {CVT_V1724_DUMMY32_ADD,                                 CVT_V1724_DUMMY32_AM,                           CVT_V1724_DUMMY32_DATA_SIZE},                                   
        {CVT_V1724_POST_TRIG_ADD,                               CVT_V1724_POST_TRIG_AM,                         CVT_V1724_POST_TRIG_DATA_SIZE},                                 
        {CVT_V1724_FRONT_PANEL_IO_ADD,                  CVT_V1724_FRONT_PANEL_IO_AM,            CVT_V1724_FRONT_PANEL_IO_DATA_SIZE},                    
        {CVT_V1724_FRONT_PANEL_IO_CTRL_ADD,             CVT_V1724_FRONT_PANEL_IO_CTRL_AM,       CVT_V1724_FRONT_PANEL_IO_CTRL_DATA_SIZE},               
//
// CH 0
        {CVT_V1724_CH0_THRESHOLD_ADD,                   CVT_V1724_CH0_THRESHOLD_AM,                     CVT_V1724_CH0_THRESHOLD_DATA_SIZE},                             
        {CVT_V1724_CH0_THR_SAMPLE_ADD,                  CVT_V1724_CH0_THR_SAMPLE_AM,            CVT_V1724_CH0_THR_SAMPLE_DATA_SIZE},                    
        {CVT_V1724_CH0_STATUS_ADD,                              CVT_V1724_CH0_STATUS_AM,                        CVT_V1724_CH0_STATUS_DATA_SIZE},                                
        {CVT_V1724_CH0_FW_REV_ADD,                              CVT_V1724_CH0_FW_REV_AM,                        CVT_V1724_CH0_FW_REV_DATA_SIZE},                                
        {CVT_V1724_CH0_READ_BLK_TRIG_ADD,               CVT_V1724_CH0_READ_BLK_TRIG_AM,         CVT_V1724_CH0_READ_BLK_TRIG_DATA_SIZE},                 
        {CVT_V1724_CH0_BLK_WRI_NUM_ADD,                 CVT_V1724_CH0_BLK_WRI_NUM_AM,           CVT_V1724_CH0_BLK_WRI_NUM_DATA_SIZE},                   
        {CVT_V1724_CH0_DAC_CONF_ADD,                    CVT_V1724_CH0_DAC_CONF_AM,                      CVT_V1724_CH0_DAC_CONF_DATA_SIZE},                              
        {CVT_V1724_CH0_CONF_ADD,                                CVT_V1724_CH0_CONF_AM,                          CVT_V1724_CH0_CONF_DATA_SIZE},                                  
        {CVT_V1724_CH0_DEBUG_ADD,                               CVT_V1724_CH0_DEBUG_AM,                         CVT_V1724_CH0_DEBUG_DATA_SIZE},                                 
//
// CH 1
        {CVT_V1724_CH1_THRESHOLD_ADD,                   CVT_V1724_CH1_THRESHOLD_AM,                     CVT_V1724_CH1_THRESHOLD_DATA_SIZE},                             
        {CVT_V1724_CH1_THR_SAMPLE_ADD,                  CVT_V1724_CH1_THR_SAMPLE_AM,            CVT_V1724_CH1_THR_SAMPLE_DATA_SIZE},                    
        {CVT_V1724_CH1_STATUS_ADD,                              CVT_V1724_CH1_STATUS_AM,                        CVT_V1724_CH1_STATUS_DATA_SIZE},                                
        {CVT_V1724_CH1_FW_REV_ADD,                              CVT_V1724_CH1_FW_REV_AM,                        CVT_V1724_CH1_FW_REV_DATA_SIZE},                                
        {CVT_V1724_CH1_READ_BLK_TRIG_ADD,               CVT_V1724_CH1_READ_BLK_TRIG_AM,         CVT_V1724_CH1_READ_BLK_TRIG_DATA_SIZE},                 
        {CVT_V1724_CH1_BLK_WRI_NUM_ADD,                 CVT_V1724_CH1_BLK_WRI_NUM_AM,           CVT_V1724_CH1_BLK_WRI_NUM_DATA_SIZE},                   
        {CVT_V1724_CH1_DAC_CONF_ADD,                    CVT_V1724_CH1_DAC_CONF_AM,                      CVT_V1724_CH1_DAC_CONF_DATA_SIZE},                              
        {CVT_V1724_CH1_CONF_ADD,                                CVT_V1724_CH1_CONF_AM,                          CVT_V1724_CH1_CONF_DATA_SIZE},                                  
        {CVT_V1724_CH1_DEBUG_ADD,                               CVT_V1724_CH1_DEBUG_AM,                         CVT_V1724_CH1_DEBUG_DATA_SIZE},                                 
//
// CH 2
        {CVT_V1724_CH2_THRESHOLD_ADD,                   CVT_V1724_CH2_THRESHOLD_AM,                     CVT_V1724_CH2_THRESHOLD_DATA_SIZE},                             
        {CVT_V1724_CH2_THR_SAMPLE_ADD,                  CVT_V1724_CH2_THR_SAMPLE_AM,            CVT_V1724_CH2_THR_SAMPLE_DATA_SIZE},                    
        {CVT_V1724_CH2_STATUS_ADD,                              CVT_V1724_CH2_STATUS_AM,                        CVT_V1724_CH2_STATUS_DATA_SIZE},                                
        {CVT_V1724_CH2_FW_REV_ADD,                              CVT_V1724_CH2_FW_REV_AM,                        CVT_V1724_CH2_FW_REV_DATA_SIZE},                                
        {CVT_V1724_CH2_READ_BLK_TRIG_ADD,               CVT_V1724_CH2_READ_BLK_TRIG_AM,         CVT_V1724_CH2_READ_BLK_TRIG_DATA_SIZE},                 
        {CVT_V1724_CH2_BLK_WRI_NUM_ADD,                 CVT_V1724_CH2_BLK_WRI_NUM_AM,           CVT_V1724_CH2_BLK_WRI_NUM_DATA_SIZE},                   
        {CVT_V1724_CH2_DAC_CONF_ADD,                    CVT_V1724_CH2_DAC_CONF_AM,                      CVT_V1724_CH2_DAC_CONF_DATA_SIZE},                              
        {CVT_V1724_CH2_CONF_ADD,                                CVT_V1724_CH2_CONF_AM,                          CVT_V1724_CH2_CONF_DATA_SIZE},                                  
        {CVT_V1724_CH2_DEBUG_ADD,                               CVT_V1724_CH2_DEBUG_AM,                         CVT_V1724_CH2_DEBUG_DATA_SIZE},                                 
//
// CH 3
        {CVT_V1724_CH3_THRESHOLD_ADD,                   CVT_V1724_CH3_THRESHOLD_AM,                     CVT_V1724_CH3_THRESHOLD_DATA_SIZE},                             
        {CVT_V1724_CH3_THR_SAMPLE_ADD,                  CVT_V1724_CH3_THR_SAMPLE_AM,            CVT_V1724_CH3_THR_SAMPLE_DATA_SIZE},                    
        {CVT_V1724_CH3_STATUS_ADD,                              CVT_V1724_CH3_STATUS_AM,                        CVT_V1724_CH3_STATUS_DATA_SIZE},                                
        {CVT_V1724_CH3_FW_REV_ADD,                              CVT_V1724_CH3_FW_REV_AM,                        CVT_V1724_CH3_FW_REV_DATA_SIZE},                                
        {CVT_V1724_CH3_READ_BLK_TRIG_ADD,               CVT_V1724_CH3_READ_BLK_TRIG_AM,         CVT_V1724_CH3_READ_BLK_TRIG_DATA_SIZE},                 
        {CVT_V1724_CH3_BLK_WRI_NUM_ADD,                 CVT_V1724_CH3_BLK_WRI_NUM_AM,           CVT_V1724_CH3_BLK_WRI_NUM_DATA_SIZE},                   
        {CVT_V1724_CH3_DAC_CONF_ADD,                    CVT_V1724_CH3_DAC_CONF_AM,                      CVT_V1724_CH3_DAC_CONF_DATA_SIZE},                              
        {CVT_V1724_CH3_CONF_ADD,                                CVT_V1724_CH3_CONF_AM,                          CVT_V1724_CH3_CONF_DATA_SIZE},                                  
        {CVT_V1724_CH3_DEBUG_ADD,                               CVT_V1724_CH3_DEBUG_AM,                         CVT_V1724_CH3_DEBUG_DATA_SIZE},                                 
//
// CH 4
        {CVT_V1724_CH4_THRESHOLD_ADD,                   CVT_V1724_CH4_THRESHOLD_AM,                     CVT_V1724_CH4_THRESHOLD_DATA_SIZE},                             
        {CVT_V1724_CH4_THR_SAMPLE_ADD,                  CVT_V1724_CH4_THR_SAMPLE_AM,            CVT_V1724_CH4_THR_SAMPLE_DATA_SIZE},                    
        {CVT_V1724_CH4_STATUS_ADD,                              CVT_V1724_CH4_STATUS_AM,                        CVT_V1724_CH4_STATUS_DATA_SIZE},                                
        {CVT_V1724_CH4_FW_REV_ADD,                              CVT_V1724_CH4_FW_REV_AM,                        CVT_V1724_CH4_FW_REV_DATA_SIZE},                                
        {CVT_V1724_CH4_READ_BLK_TRIG_ADD,               CVT_V1724_CH4_READ_BLK_TRIG_AM,         CVT_V1724_CH4_READ_BLK_TRIG_DATA_SIZE},                 
        {CVT_V1724_CH4_BLK_WRI_NUM_ADD,                 CVT_V1724_CH4_BLK_WRI_NUM_AM,           CVT_V1724_CH4_BLK_WRI_NUM_DATA_SIZE},                   
        {CVT_V1724_CH4_DAC_CONF_ADD,                    CVT_V1724_CH4_DAC_CONF_AM,                      CVT_V1724_CH4_DAC_CONF_DATA_SIZE},                              
        {CVT_V1724_CH4_CONF_ADD,                                CVT_V1724_CH4_CONF_AM,                          CVT_V1724_CH4_CONF_DATA_SIZE},                                  
        {CVT_V1724_CH4_DEBUG_ADD,                               CVT_V1724_CH4_DEBUG_AM,                         CVT_V1724_CH4_DEBUG_DATA_SIZE},                                 
//
// CH 5
        {CVT_V1724_CH5_THRESHOLD_ADD,                   CVT_V1724_CH5_THRESHOLD_AM,                     CVT_V1724_CH5_THRESHOLD_DATA_SIZE},                             
        {CVT_V1724_CH5_THR_SAMPLE_ADD,                  CVT_V1724_CH5_THR_SAMPLE_AM,            CVT_V1724_CH5_THR_SAMPLE_DATA_SIZE},                    
        {CVT_V1724_CH5_STATUS_ADD,                              CVT_V1724_CH5_STATUS_AM,                        CVT_V1724_CH5_STATUS_DATA_SIZE},                                
        {CVT_V1724_CH5_FW_REV_ADD,                              CVT_V1724_CH5_FW_REV_AM,                        CVT_V1724_CH5_FW_REV_DATA_SIZE},                                
        {CVT_V1724_CH5_READ_BLK_TRIG_ADD,               CVT_V1724_CH5_READ_BLK_TRIG_AM,         CVT_V1724_CH5_READ_BLK_TRIG_DATA_SIZE},                 
        {CVT_V1724_CH5_BLK_WRI_NUM_ADD,                 CVT_V1724_CH5_BLK_WRI_NUM_AM,           CVT_V1724_CH5_BLK_WRI_NUM_DATA_SIZE},                   
        {CVT_V1724_CH5_DAC_CONF_ADD,                    CVT_V1724_CH5_DAC_CONF_AM,                      CVT_V1724_CH5_DAC_CONF_DATA_SIZE},                              
        {CVT_V1724_CH5_CONF_ADD,                                CVT_V1724_CH5_CONF_AM,                          CVT_V1724_CH5_CONF_DATA_SIZE},                                  
        {CVT_V1724_CH5_DEBUG_ADD,                               CVT_V1724_CH5_DEBUG_AM,                         CVT_V1724_CH5_DEBUG_DATA_SIZE},                                 
//
// CH 6
        {CVT_V1724_CH6_THRESHOLD_ADD,                   CVT_V1724_CH6_THRESHOLD_AM,                     CVT_V1724_CH6_THRESHOLD_DATA_SIZE},                             
        {CVT_V1724_CH6_THR_SAMPLE_ADD,                  CVT_V1724_CH6_THR_SAMPLE_AM,            CVT_V1724_CH6_THR_SAMPLE_DATA_SIZE},                    
        {CVT_V1724_CH6_STATUS_ADD,                              CVT_V1724_CH6_STATUS_AM,                        CVT_V1724_CH6_STATUS_DATA_SIZE},                                
        {CVT_V1724_CH6_FW_REV_ADD,                              CVT_V1724_CH6_FW_REV_AM,                        CVT_V1724_CH6_FW_REV_DATA_SIZE},                                
        {CVT_V1724_CH6_READ_BLK_TRIG_ADD,               CVT_V1724_CH6_READ_BLK_TRIG_AM,         CVT_V1724_CH6_READ_BLK_TRIG_DATA_SIZE},                 
        {CVT_V1724_CH6_BLK_WRI_NUM_ADD,                 CVT_V1724_CH6_BLK_WRI_NUM_AM,           CVT_V1724_CH6_BLK_WRI_NUM_DATA_SIZE},                   
        {CVT_V1724_CH6_DAC_CONF_ADD,                    CVT_V1724_CH6_DAC_CONF_AM,                      CVT_V1724_CH6_DAC_CONF_DATA_SIZE},                              
        {CVT_V1724_CH6_CONF_ADD,                                CVT_V1724_CH6_CONF_AM,                          CVT_V1724_CH6_CONF_DATA_SIZE},                                  
        {CVT_V1724_CH6_DEBUG_ADD,                               CVT_V1724_CH6_DEBUG_AM,                         CVT_V1724_CH6_DEBUG_DATA_SIZE},                                 
//
// CH 7
        {CVT_V1724_CH7_THRESHOLD_ADD,                   CVT_V1724_CH7_THRESHOLD_AM,                     CVT_V1724_CH7_THRESHOLD_DATA_SIZE},                             
        {CVT_V1724_CH7_THR_SAMPLE_ADD,                  CVT_V1724_CH7_THR_SAMPLE_AM,            CVT_V1724_CH7_THR_SAMPLE_DATA_SIZE},                    
        {CVT_V1724_CH7_STATUS_ADD,                              CVT_V1724_CH7_STATUS_AM,                        CVT_V1724_CH7_STATUS_DATA_SIZE},                                
        {CVT_V1724_CH7_FW_REV_ADD,                              CVT_V1724_CH7_FW_REV_AM,                        CVT_V1724_CH7_FW_REV_DATA_SIZE},                                
        {CVT_V1724_CH7_READ_BLK_TRIG_ADD,               CVT_V1724_CH7_READ_BLK_TRIG_AM,         CVT_V1724_CH7_READ_BLK_TRIG_DATA_SIZE},                 
        {CVT_V1724_CH7_BLK_WRI_NUM_ADD,                 CVT_V1724_CH7_BLK_WRI_NUM_AM,           CVT_V1724_CH7_BLK_WRI_NUM_DATA_SIZE},                   
        {CVT_V1724_CH7_DAC_CONF_ADD,                    CVT_V1724_CH7_DAC_CONF_AM,                      CVT_V1724_CH7_DAC_CONF_DATA_SIZE},                              
        {CVT_V1724_CH7_CONF_ADD,                                CVT_V1724_CH7_CONF_AM,                          CVT_V1724_CH7_CONF_DATA_SIZE},                                  
        {CVT_V1724_CH7_DEBUG_ADD,                               CVT_V1724_CH7_DEBUG_AM,                         CVT_V1724_CH7_DEBUG_DATA_SIZE},                                 
};

// Static methods declaration

// Global visible variables declaration

//
//     B O A R D S   H A N D L I N G
//

// 
BOOL cvt_V1724_open( cvt_V1724_data* p_data, UINT16 base_address, long vme_handle)
{
        memset( p_data, 0, sizeof( cvt_V1724_data));

        // basic data initialization
        if( !cvt_board_open( &p_data->m_common_data, base_address, vme_handle, CVT_V1724_REG_TABLE))
                return FALSE;
        // board specific data initialization
        p_data->m_common_data.set_MCST_CBLT= ( BOOL (*)( void*, UINT8, MCST_CBLT_board_pos))cvt_V1724_set_MCST_CBLT;

        // preallocate a suitable memory chunck for sample temporary storage
        p_data->m_tmp_sample_buffer_size= 16*1024;
        p_data->m_tmp_sample_buffer= malloc( p_data->m_tmp_sample_buffer_size* sizeof( UINT32));

        // HACK: to be debugged
        //if( !cvt_V1724_software_reset( p_data))
        //{
        //      TRACE( "cvt_V1724_open: error resetting board !\n");
        //      return FALSE;
        //}

        return TRUE;
}

// 
BOOL cvt_V1724_close( cvt_V1724_data* p_data)
{
        if( p_data->m_tmp_sample_buffer)
        {
                free( p_data->m_tmp_sample_buffer);
                p_data->m_tmp_sample_buffer= NULL;
                p_data->m_tmp_sample_buffer_size= 0;
        }
        if( !cvt_board_close( &p_data->m_common_data))
                return FALSE;
        return TRUE;
}

//
//     L E V E L   0   A P I s
//


//
//     L E V E L   1   A P I s
//

//
//     L E V E L   2   A P I s
//


// 
BOOL cvt_V1724_read_buffer( cvt_V1724_data* p_data, UINT8 ch_index, UINT16* p_buff, UINT32* p_buff_size)
{
        static const UINT16 READ_BLK_TRIG[ CVT_V1724_MAX_CHANNEL]=
        {
                CVT_V1724_CH0_READ_BLK_TRIG_INDEX,                              
                CVT_V1724_CH1_READ_BLK_TRIG_INDEX,                              
                CVT_V1724_CH2_READ_BLK_TRIG_INDEX,                              
                CVT_V1724_CH3_READ_BLK_TRIG_INDEX,                              
                CVT_V1724_CH4_READ_BLK_TRIG_INDEX,                              
                CVT_V1724_CH5_READ_BLK_TRIG_INDEX,                              
                CVT_V1724_CH6_READ_BLK_TRIG_INDEX,                              
                CVT_V1724_CH7_READ_BLK_TRIG_INDEX,                              
        };

        static const UINT16 BLK_WRI_NUM[ CVT_V1724_MAX_CHANNEL]=
        {
                CVT_V1724_CH0_BLK_WRI_NUM_INDEX,                                
                CVT_V1724_CH1_BLK_WRI_NUM_INDEX,                                
                CVT_V1724_CH2_BLK_WRI_NUM_INDEX,                                
                CVT_V1724_CH3_BLK_WRI_NUM_INDEX,                                
                CVT_V1724_CH4_BLK_WRI_NUM_INDEX,                                
                CVT_V1724_CH5_BLK_WRI_NUM_INDEX,                                
                CVT_V1724_CH6_BLK_WRI_NUM_INDEX,                                
                CVT_V1724_CH7_BLK_WRI_NUM_INDEX,                                
        };

        UINT32 reg_value= 0;
        UINT32 num_blocks= 0;

        //
        // input param check
        if( ch_index>= CVT_V1724_MAX_CHANNEL)
        {
                TRACE1( "V1724 cvt_V1724_read_buffer bad channel '%d'!\n", ch_index);
                return FALSE;
        }
        //
        // read the number of events ready
        if( !cvt_read_reg( &p_data->m_common_data, BLK_WRI_NUM[ ch_index], &num_blocks))
        {
                TRACE1( "V1724 cvt_V1724_read_buffer BLK_WRI_NUM[%d] read failed !\n", ch_index);
                return FALSE;
        }
        if( !num_blocks)
        {
                *p_buff_size= 0;
                return TRUE;
        }
        //
        // read the number of entries ready 
#define __FIFO_BLT
#ifdef __FIFO_BLT
        {
                UINT32 samples_to_read= 0;
                UINT32 read= 0;
                UINT32 i; 
                if( !cvt_FIFO_BLT_read_reg( &p_data->m_common_data, READ_BLK_TRIG[ ch_index], &reg_value, 1* sizeof( UINT32), &read))
                {
                        TRACE1( "V1724 cvt_V1724_read_buffer READ_BLK_TRIG[%d] read failed !\n", ch_index);
                        return FALSE;
                }
                if( !read)
                {
                        *p_buff_size= 0;
                        return TRUE;
                }
                // Get the samples' number (16bit word)
                samples_to_read= reg_value<< 1;
                if( !samples_to_read)
                {
                        *p_buff_size= 0;
                        return TRUE;
                }
                if( samples_to_read> 1024*1024)
                {
                        // ????
                        // Remove blocks
                        if( !cvt_write( &p_data->m_common_data, p_data->m_common_data.m_p_reg_table[ CVT_V1724_BROAD_CH_BLK_REM_NUM_INDEX].m_address, &num_blocks, p_data->m_common_data.m_p_reg_table[ CVT_V1724_BROAD_CH_BLK_REM_NUM_INDEX].m_am, p_data->m_common_data.m_p_reg_table[ CVT_V1724_BROAD_CH_BLK_REM_NUM_INDEX].m_data_size))
                        {
                                TRACE1( "V1724 cvt_V1724_read_buffer READ_BLK_TRIG[%d] read failed !\n", ch_index);
                        }
                        return FALSE;
                }
                if( ( samples_to_read>>1 )> p_data->m_tmp_sample_buffer_size)
                {
                        p_data->m_tmp_sample_buffer_size= samples_to_read>> 1;
                        p_data->m_tmp_sample_buffer= realloc( p_data->m_tmp_sample_buffer, p_data->m_tmp_sample_buffer_size* sizeof( UINT32));
                }
                if( !cvt_FIFO_BLT_read_reg( &p_data->m_common_data, READ_BLK_TRIG[ ch_index], p_data->m_tmp_sample_buffer, samples_to_read* sizeof( UINT16), &read))
                {
                        TRACE1( "V1724 cvt_V1724_read_buffer READ_BLK_TRIG[%d] read failed !\n", ch_index);
                        return FALSE;
                }
                if( !read)
                {
                        *p_buff_size= 0;
                        return TRUE;
                }
                read>>= 1;
                if( *p_buff_size> read)
                {
                        *p_buff_size= read;
                }
                for( i= 0; i< ((*p_buff_size)>> 1); i++)
                {
                        p_buff[ i<< 1]= p_data->m_tmp_sample_buffer[i]& 0xffff;
                        p_buff[ (i<< 1)+ 1]= (p_data->m_tmp_sample_buffer[i]>> 16)& 0xffff;
                }
        }
#else
        if( !cvt_read( &p_data->m_common_data, p_data->m_common_data.m_p_reg_table[ READ_BLK_TRIG[ ch_index]].m_address, &reg_value, cvA32_S_DATA, cvD32))
        {
                TRACE1( "V1724 cvt_V1724_read_buffer READ_BLK_TRIG[%d] read failed !\n", ch_index);
                return FALSE;
        }
        {
                UINT32 samples_to_read= 0;
                UINT32 read= 0;
                UINT32 i; 
                // Get the samples' number (16bit word)
                samples_to_read= reg_value<< 1;
                if( !samples_to_read)
                {
                        *p_buff_size= 0;
                        return TRUE;
                }
                if( samples_to_read> 128*1024)
                {
                        // ????
                        // Remove blocks
                        if( !cvt_write( &p_data->m_common_data, p_data->m_common_data.m_p_reg_table[ CVT_V1724_BROAD_CH_BLK_REM_NUM_INDEX].m_address, &num_blocks, p_data->m_common_data.m_p_reg_table[ CVT_V1724_BROAD_CH_BLK_REM_NUM_INDEX].m_am, p_data->m_common_data.m_p_reg_table[ CVT_V1724_BROAD_CH_BLK_REM_NUM_INDEX].m_data_size))
                        {
                                TRACE1( "V1724 cvt_V1724_read_buffer READ_BLK_TRIG[%d] read failed !\n", ch_index);
                        }
                        return FALSE;
                }
                if( samples_to_read> p_data->m_tmp_sample_buffer_size)
                {
                        p_data->m_tmp_sample_buffer_size= samples_to_read;
                        p_data->m_tmp_sample_buffer= realloc( p_data->m_tmp_sample_buffer, p_data->m_tmp_sample_buffer_size* sizeof( UINT32));
                }

                if( *p_buff_size> samples_to_read)
                {
                        *p_buff_size= samples_to_read;
                }
                for( i= 0; ( i< samples_to_read); i+= 2)
                {
                        if( !cvt_read( &p_data->m_common_data, p_data->m_common_data.m_p_reg_table[ READ_BLK_TRIG[ ch_index]].m_address, &reg_value, cvA32_S_DATA, cvD32))
                        {
                                TRACE1( "V1724 cvt_V1724_read_buffer READ_BLK_TRIG[%d] read failed !\n", ch_index);
                                return FALSE;
                        }
                        if( i>= (*p_buff_size- 1))
                                continue;
                        p_buff[ i]= reg_value& 0xffff;
                        p_buff[ i+ 1]= (reg_value>> 16)& 0xffff;
                        //if( !cvt_read( &p_data->m_common_data, p_data->m_common_data.m_p_reg_table[ READ_BLK_TRIG[ ch_index]].m_address, &p_buff[ i], cvA32_S_DATA, cvD32))
                        //{
                        //      TRACE1( "V1724 cvt_V1724_read_buffer READ_BLK_TRIG[%d] read failed !\n", ch_index);
                        //      return FALSE;
                        //}
                }
        }
#endif
        return TRUE;
}

//
BOOL cvt_V1724_set_trigger_mode( cvt_V1724_data* p_data, BOOL falling_edge_enable, BOOL trigger_in_enable, BOOL trigger_out_enable, BOOL ext_trigger_enable, BOOL sw_trigger_enable, UINT8 ch_trigger_enable_msk, BOOL trigger_overlap_enable, UINT32 post_trigger)
{
        static const UINT16 CH_TRIGGER_MSK[ CVT_V1724_MAX_CHANNEL]=
        {
                CVT_V1724_TRGEN_CH0_MSK,                
                CVT_V1724_TRGEN_CH1_MSK,                
                CVT_V1724_TRGEN_CH2_MSK,                
                CVT_V1724_TRGEN_CH3_MSK,                
                CVT_V1724_TRGEN_CH4_MSK,                
                CVT_V1724_TRGEN_CH5_MSK,                
                CVT_V1724_TRGEN_CH6_MSK,                
                CVT_V1724_TRGEN_CH7_MSK,                
        };

        UINT16 set_msk16= 0;
        UINT16 clear_msk16= 0;
        UINT32 set_msk32= 0;
        UINT32 clear_msk32= 0;

        //
        // falling/rising edge enable ( Over/Under threshold)
        set_msk32|= ( !falling_edge_enable)? 0: CVT_V1724_CHCTRL_TRG_OUT_UNDER_EN_MSK;
        clear_msk32|= ( !falling_edge_enable)? CVT_V1724_CHCTRL_TRG_OUT_UNDER_EN_MSK: 0;
        //
        // trigger input enable
        set_msk32|= ( trigger_in_enable)? CVT_V1724_CHCTRL_TRG_IN_EN_MSK: 0;
        clear_msk32|= ( trigger_in_enable)? 0: CVT_V1724_CHCTRL_TRG_IN_EN_MSK;
        //
        // trigger output enable
        set_msk32|= ( trigger_out_enable)? CVT_V1724_CHCTRL_TRG_OUT_EN_MSK: 0;
        clear_msk32|= ( trigger_out_enable)? 0: CVT_V1724_CHCTRL_TRG_OUT_EN_MSK;
        
        //
        // setup each channel
        if( set_msk32)
        {
                if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_SET_CTRL_INDEX, &set_msk32))
                {
                        TRACE( "V1724 BROADCAST CH CTRL write failed !\n");
                        return FALSE;
                }
        }
        if( clear_msk32)
        {
                if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_CLEAR_CTRL_INDEX, &clear_msk32))
                {
                        TRACE( "V1724 BROADCAST CH CTRL write failed !\n");
                        return FALSE;
                }
        }

        //
        // Global Channel trigger enable
        set_msk16|= ( ch_trigger_enable_msk)? CVT_V1724_TRGEN_ENABLE_MSK: 0;

        //
        // External trigger
        set_msk16|= ( ext_trigger_enable)? CVT_V1724_TRGEN_EXT_MSK: 0;
        clear_msk16|= ( ext_trigger_enable)? 0: CVT_V1724_TRGEN_EXT_MSK;
        //
        // Software trigger
        set_msk16|= ( sw_trigger_enable)? CVT_V1724_TRGEN_SW_MSK: 0;
        clear_msk16|= ( sw_trigger_enable)? 0: CVT_V1724_TRGEN_SW_MSK;
        // 
        // Trigger Overlap
        set_msk16|= ( trigger_overlap_enable)? CVT_V1724_CHCTRL_TRG_OVERLAP_MSK: 0;
        clear_msk16|= ( trigger_overlap_enable)? 0: CVT_V1724_CHCTRL_TRG_OVERLAP_MSK;

        //
        // Channels' trigger
        {
                int i;
                for( i= 0; i< CVT_V1724_MAX_CHANNEL ; i++, ch_trigger_enable_msk>>= 1)
                {
                        if( ch_trigger_enable_msk& 0x01)
                        {
                                set_msk16|= CH_TRIGGER_MSK[ i];
                        }
                        else
                        {
                                clear_msk16|= CH_TRIGGER_MSK[ i];
                        }
                }
        }
        //
        // bitmask set
        if( set_msk16)
        {
                if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1724_TRIGGER_ENABLE_INDEX, &set_msk16))
                {
                        TRACE( "V1724 CVT_V1724_TRIGGER_ENABLE write failed !\n");
                        return FALSE;
                }
        }
        //
        // bitmask clear
        if( clear_msk16)
        {
                // clear the enable bit
                if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1724_TRIGGER_ENABLE_INDEX, &clear_msk16))
                {
                        TRACE( "V1724 CVT_V1724_TRIGGER_ENABLE write failed !\n");
                        return FALSE;
                }
        }

        //
        // Post Trigger
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_POST_TRIG_INDEX, &post_trigger))
        {
                TRACE( "V1724 CVT_V1724_POST_TRIG write failed !\n");
                return FALSE;
        }
        
        return TRUE;
}

//
BOOL cvt_V1724_set_acquisition_mode( cvt_V1724_data* p_data, BOOL sample_enable, CVT_V1724_CH_BLKSIZE block_size)
{
        UINT32 set_msk= 0;
        UINT32 clear_msk= 0;

        //
        // parameter checking
        switch( block_size)
        {
        case CVT_V1724_CHBKSZ_512:                              
        case CVT_V1724_CHBKSZ_1K:                               
        case CVT_V1724_CHBKSZ_2K:                               
        case CVT_V1724_CHBKSZ_4K:                               
        case CVT_V1724_CHBKSZ_8K:                               
        case CVT_V1724_CHBKSZ_16K:                              
        case CVT_V1724_CHBKSZ_32K:                              
        case CVT_V1724_CHBKSZ_64K:                              
        case CVT_V1724_CHBKSZ_128K:                             
        case CVT_V1724_CHBKSZ_256K:                             
        case CVT_V1724_CHBKSZ_512K:                             
                break;
        default:
                TRACE1( "V1724 Bad block size '%d'!\n", block_size);
                return FALSE;
        }
        //
        // Sample enable
        set_msk|= ( sample_enable)? CVT_V1724_CHCTRL_SAMPLE_ACQ_MSK: 0;
        clear_msk|= ( sample_enable)? 0: CVT_V1724_CHCTRL_SAMPLE_ACQ_MSK;
        
        //
        // setup each channel
        if( set_msk)
        {
                if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_SET_CTRL_INDEX, &set_msk))
                {
                        TRACE( "V1724 CH SET CONTROL write failed !\n");
                        return FALSE;
                }
        }
        if( clear_msk)
        {
                if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_CLEAR_CTRL_INDEX, &clear_msk))
                {
                        TRACE( "V1724 CH CLEAR CONTROL write failed !\n");
                        return FALSE;
                }               
        }
        //
        // Block size   
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_BLKSIZE_INDEX, &block_size))
        {
                TRACE( "V1724 CH BLOCK SIZE write failed !\n");
                return FALSE;
        }               
        return TRUE;
}

//
BOOL cvt_V1724_set_dither_enable( cvt_V1724_data* p_data, UINT8 ch_msk, BOOL dither_value)
{
        static const UINT16 CH_CONF[ CVT_V1724_MAX_CHANNEL]=
        {
                CVT_V1724_CH0_CONF_INDEX,                       
                CVT_V1724_CH1_CONF_INDEX,                       
                CVT_V1724_CH2_CONF_INDEX,                       
                CVT_V1724_CH3_CONF_INDEX,                       
                CVT_V1724_CH4_CONF_INDEX,                       
                CVT_V1724_CH5_CONF_INDEX,                       
                CVT_V1724_CH6_CONF_INDEX,                       
                CVT_V1724_CH7_CONF_INDEX,                       
        };
        UINT16 set_msk= 0;
        //
        // Dither enable
        set_msk|= CVT_V1724_CHCONF_DITHER_MSK;

        if( dither_value)
        {
                int i;
                for( i= 0; (i< CVT_V1724_MAX_CHANNEL )&& ch_msk; i++, ch_msk>>= 1)
                {
                        if( !(ch_msk& 0x01))
                                continue;
                        if( !cvt_set_bitmask_reg( &p_data->m_common_data, CH_CONF[ i], &set_msk))
                        {
                                TRACE( "V1724 CH CONF write failed !\n");
                                return FALSE;
                        }
                }
        }
        else
        {
                int i;
                for( i= 0; (i< CVT_V1724_MAX_CHANNEL )&& ch_msk; i++, ch_msk>>= 1)
                {
                        if( !(ch_msk& 0x01))
                                continue;
                        if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CH_CONF[ i], &set_msk))
                        {
                                TRACE( "V1724 CH CONF write failed !\n");
                                return FALSE;
                        }
                }
        }
        return TRUE;
}

//
BOOL cvt_V1724_set_interrupt( cvt_V1724_data* p_data, UINT8 level, UINT8 vector, UINT8 event_number)
{
        UINT16 reg_value;
        //
        // interrupt level
        reg_value= level& 0x07;
        if( level!= reg_value)
        {
                TRACE( "V1724 bad interrupt level !\n");
                return FALSE;
        }
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_INT_LEVEL_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_INT_LEVEL write failed !\n");
                return FALSE;
        }
        //
        // interrupt vector
        reg_value= vector;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_INT_VECTOR_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_INT_VECTOR write failed !\n");
                return FALSE;
        }
/* HACK: not jet implemented onto board fpga
        //
        // event number (event trigger register)
        reg_value= event_number& 0x1f;
        if( event_number!= reg_value)
        {
                TRACE( "V1724 bad interrupt event number !\n");
                return FALSE;
        }
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_EVENT_TRG_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_EVENT_TRG write failed !\n");
                return FALSE;
        }
*/
        return TRUE;
}

//
BOOL cvt_V1724_set_readout_mode( cvt_V1724_data* p_data, BOOL enable_bus_error, UINT16 BLT_event_number)
{
        UINT16 set_msk= 0;
        UINT16 clear_msk= 0;
        
        //
        // Bus error
        set_msk|= ( enable_bus_error)? CVT_V1724_CTRL_BERR_ENABLE_MSK: 0;
        clear_msk|= ( enable_bus_error)? 0: CVT_V1724_CTRL_BERR_ENABLE_MSK;
        
        //
        // bitmask set
        if( set_msk)
        {
                if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1724_CONTROL_INDEX, &set_msk))
                {
                        TRACE( "V1724 CVT_V1724_CONTROL write failed !\n");
                        return FALSE;
                }
        }
        //
        // bitmask clear
        if( clear_msk)
        {
                // clear the enable bit
                if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1724_CONTROL_INDEX, &clear_msk))
                {
                        TRACE( "V1724 CVT_V1724_CONTROL write failed !\n");
                        return FALSE;
                }
        }

        // 
        // BLT event number
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BLT_EVENT_NUM_INDEX, &BLT_event_number))
        {
                TRACE( "V1724 CVT_V1724_BLT_EVENT_NUM write failed !\n");
                return FALSE;
        }

        return TRUE;
}

// 
BOOL cvt_V1724_software_reset( cvt_V1724_data* p_data)
{
        //
        // Write CVT_V1724_SW_RESET register
        UINT16 reg_value= 0;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_SW_RESET_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_SW_RESET write failed !\n");
                return FALSE;
        }
        return TRUE;
}

//
BOOL cvt_V1724_data_clear( cvt_V1724_data* p_data)
{
        //
        // Write CVT_V1724_SW_RESET register
        UINT16 reg_value= 0;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_SW_CLEAR_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_CLEAR_RESET write failed !\n");
                return FALSE;
        }
        return TRUE;
}

//
BOOL cvt_V1724_set_channel_offset( cvt_V1724_data* p_data, UINT8 ch_msk, UINT16 offset_value)
{
        static const UINT16 CH_DAC_CONF[ CVT_V1724_MAX_CHANNEL]=
        {
                CVT_V1724_CH0_DAC_CONF_INDEX,           
                CVT_V1724_CH1_DAC_CONF_INDEX,           
                CVT_V1724_CH2_DAC_CONF_INDEX,           
                CVT_V1724_CH3_DAC_CONF_INDEX,           
                CVT_V1724_CH4_DAC_CONF_INDEX,           
                CVT_V1724_CH5_DAC_CONF_INDEX,           
                CVT_V1724_CH6_DAC_CONF_INDEX,           
                CVT_V1724_CH7_DAC_CONF_INDEX,           
        };
        UINT32 reg_value_A= 0, reg_value_B= 0;
        //
        // Channel offset

        //
        // Data for DAC A ( even channels)
        CVT_V1724_SET_CH_DAC_CONF( reg_value_A, offset_value);
        reg_value_A|= CVT_V1724_CHDAC_SET_A_MSK;
        //
        // Data for DAC B ( odd channels)
        CVT_V1724_SET_CH_DAC_CONF( reg_value_B, offset_value);
        reg_value_B|= CVT_V1724_CHDAC_SET_B_MSK;
        
        //
        // setup each channel
        {
                int i;
                for( i= 0; (i< CVT_V1724_MAX_CHANNEL )&& ch_msk; i++, ch_msk>>= 1)
                {
                        if( ch_msk& 0x01)
                        {
                                //
                                // Wait for DAC !busy
                                BOOL trash;
                                BOOL is_dac_busy= TRUE;
                                while( is_dac_busy)
                                {
                                        // HACK insert timeout here

                                        if( !cvt_V1724_get_channel_status( p_data, i, &is_dac_busy, &trash, &trash, &trash))
                                        {
                                                TRACE( "V1724 set channel offset failed !\n");
                                                return FALSE;
                                        }
                                }
                                if( !cvt_write_reg( &p_data->m_common_data, CH_DAC_CONF[ i], ( i& 0x01)? &reg_value_B: &reg_value_A))
                                {
                                        TRACE( "V1724 CH DAC CONF write failed !\n");
                                        return FALSE;
                                }
                        }
                }
        }

        return TRUE;
}

//
BOOL cvt_V1724_set_channel_trigger( cvt_V1724_data* p_data, UINT8 ch_msk, UINT32 trigger_threshold, UINT32 threshold_samples)
{
        static const UINT16 CH_TRG_THR[ CVT_V1724_MAX_CHANNEL]=
        {
                CVT_V1724_CH0_THRESHOLD_INDEX,                                  
                CVT_V1724_CH1_THRESHOLD_INDEX,                                  
                CVT_V1724_CH2_THRESHOLD_INDEX,                                  
                CVT_V1724_CH3_THRESHOLD_INDEX,                                  
                CVT_V1724_CH4_THRESHOLD_INDEX,                                  
                CVT_V1724_CH5_THRESHOLD_INDEX,                                  
                CVT_V1724_CH6_THRESHOLD_INDEX,                                  
                CVT_V1724_CH7_THRESHOLD_INDEX,                                  
        };

        static const UINT16 CH_TRG_THR_SAMPLE[ CVT_V1724_MAX_CHANNEL]=
        {
                CVT_V1724_CH0_THR_SAMPLE_INDEX,                         
                CVT_V1724_CH1_THR_SAMPLE_INDEX,                         
                CVT_V1724_CH2_THR_SAMPLE_INDEX,                         
                CVT_V1724_CH3_THR_SAMPLE_INDEX,                         
                CVT_V1724_CH4_THR_SAMPLE_INDEX,                         
                CVT_V1724_CH5_THR_SAMPLE_INDEX,                         
                CVT_V1724_CH6_THR_SAMPLE_INDEX,                         
                CVT_V1724_CH7_THR_SAMPLE_INDEX,                         
        };

        //
        // trigger threshold
        {
                int i;
                UINT8 tmp_msk= ch_msk;
                UINT32 reg_value= trigger_threshold;
                for( i= 0; (i< CVT_V1724_MAX_CHANNEL )&& tmp_msk; i++, tmp_msk>>= 1)
                {
                        if( tmp_msk& 0x01)
                        {
                                if( !cvt_write_reg( &p_data->m_common_data, CH_TRG_THR[ i], &reg_value))
                                {
                                        TRACE( "V1724 CH TRIGGER THRESHOLD write failed !\n");
                                        return FALSE;
                                }
                        }
                }
        }

        //
        // trigger threshold samples
        {
                int i;
                UINT8 tmp_msk= ch_msk;
                UINT32 reg_value= threshold_samples;
                for( i= 0; (i< CVT_V1724_MAX_CHANNEL)&& tmp_msk; i++, tmp_msk>>= 1)
                {
                        if( tmp_msk& 0x01)
                        {
                                if( !cvt_write_reg( &p_data->m_common_data, CH_TRG_THR_SAMPLE[ i], &reg_value))
                                {
                                        TRACE( "V1724 CH TRIGGER THRESHOLD SAMPLES write failed !\n");
                                        return FALSE;
                                }
                        }
                }
        }
        return TRUE;
}

//
BOOL cvt_V1724_set_front_panel_IO( cvt_V1724_data* p_data, BOOL use_TTL)
{
        UINT16 set_msk= 0;
        UINT16 clear_msk= 0;
        
        //
        // Front panel control
        set_msk|= ( use_TTL)? CVT_V1724_FPIO_CTRL_TTL_MSK: 0;
        clear_msk|= ( use_TTL)? 0: CVT_V1724_FPIO_CTRL_TTL_MSK;

        //
        // bitmask set
        if( set_msk)
        {
                if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1724_FRONT_PANEL_IO_CTRL_INDEX, &set_msk))
                {
                        TRACE( "V1724 CVT_V1724_FRONT_PANEL_IO_CTRL write failed !\n");
                        return FALSE;
                }
        }
        //
        // bitmask clear
        if( clear_msk)
        {
                // clear the enable bit
                if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1724_FRONT_PANEL_IO_CTRL_INDEX, &clear_msk))
                {
                        TRACE( "V1724 CVT_V1724_FRONT_PANEL_IO_CTRL write failed !\n");
                        return FALSE;
                }
        }
        return TRUE;
}

//
BOOL cvt_V1724_software_trigger( cvt_V1724_data* p_data)
{
        UINT16 reg_value;
        //
        // software trigger
        reg_value= 1;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_SW_TRIGGER_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_SW_TRIGGER write failed !\n");
                return FALSE;
        }
        return TRUE;
}


//
BOOL cvt_V1724_get_channel_status( cvt_V1724_data* p_data, UINT8 ch_index, BOOL *p_is_dac_busy, BOOL *p_is_fifo_full, BOOL *p_is_fifo_empty, BOOL *p_is_block_remove_ok)
{
        static const UINT16 CH_STATUS[ CVT_V1724_MAX_CHANNEL]=
        {
                CVT_V1724_CH0_STATUS_INDEX,                                             
                CVT_V1724_CH1_STATUS_INDEX,                                             
                CVT_V1724_CH2_STATUS_INDEX,                                             
                CVT_V1724_CH3_STATUS_INDEX,                                             
                CVT_V1724_CH4_STATUS_INDEX,                                             
                CVT_V1724_CH5_STATUS_INDEX,                                             
                CVT_V1724_CH6_STATUS_INDEX,                                             
                CVT_V1724_CH7_STATUS_INDEX,                                             
        };

        UINT32 reg_value= 0;

        //
        // input param check
        if( ch_index>= CVT_V1724_MAX_CHANNEL)
        {
                TRACE1( "V1724 cvt_V1724_get_channel_status bad channel '%d'!\n", ch_index);
                return FALSE;
        }
        //
        // read channel status register 1
        if( !cvt_read_reg( &p_data->m_common_data, CH_STATUS[ ch_index], &reg_value))
        {
                TRACE1( "V1724 CH_STATUS[%d] read failed !\n", ch_index);
                return FALSE;
        }
        *p_is_dac_busy= ( reg_value& CVT_V1724_CHSTS_DAC_BUSY_MSK)? TRUE: FALSE;
        *p_is_fifo_full= ( reg_value& CVT_V1724_CHSTS_FIFO_FULL_MSK)? TRUE: FALSE;
        *p_is_fifo_empty= ( reg_value& CVT_V1724_CHSTS_FIFO_EMPTY_MSK)? TRUE: FALSE;
        *p_is_block_remove_ok= ( reg_value& CVT_V1724_CHSTS_BLOCK_REM_OK_MSK)? TRUE: FALSE;

        return TRUE;
}



BOOL cvt_V1724_get_system_info( cvt_V1724_data* p_data, UINT16 *p_firmware_rev, UINT16 *p_serial_number)
{
        UINT16 reg_value= 0;
        //
        // Firmware revision register
        if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_FW_REV_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FW_REV read failed !\n");
                return FALSE;
        }
        *p_firmware_rev= reg_value;
/*
        //
        // Serial number
        if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_SERIAL_LSB_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_ROM_SERIAL_LSB read failed !\n");
                return FALSE;
        }
        *p_serial_number= reg_value& 0x00ff;
        if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_SERIAL_MSB_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_ROM_SERIAL_MSB read failed !\n");
                return FALSE;
        }
        *p_serial_number|= (reg_value& 0x00ff)<< 8;
*/
        *p_serial_number= 0;

        return TRUE;
}

//
BOOL cvt_V1724_set_MCST_CBLT( cvt_V1724_data* p_data, UINT8 address, MCST_CBLT_board_pos pos)
{
        UINT16 reg_value;
        //
        // MCST/CBLT address register
        reg_value= address;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_MCST_CBLT_ADDRESS_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_MCST_CBLT_ADDRESS write failed !\n");
                return FALSE;
        }
        //
        // MCST/CBLT control register
        switch( pos)
        {
        case MCST_CBLT_board_pos_first:
                reg_value= CVT_V1724_MCCTRL_FIRST_BOARD_MSK;
                break;
        case MCST_CBLT_board_pos_mid:
                reg_value= CVT_V1724_MCCTRL_MID_BOARD_MSK;
                break;
        case MCST_CBLT_board_pos_last:
                reg_value= CVT_V1724_MCCTRL_LAST_BOARD_MSK;
                break;
        default:
                TRACE1( "V1724 cvt_V1724_set_MCST_CBLT bad position indentifier '%d'!\n", pos);
                return FALSE;
        }
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_MCST_CBLT_CTRL_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_MCST_CBLT_CTRL write failed !\n");
                return FALSE;
        }
        return TRUE;
}

//
BOOL cvt_V1724_write_flash_page( cvt_V1724_data* p_data, const UINT8* page_buff, UINT32 page_index)
{
        int i;
        UINT16 reg_value;
        UINT32 flash_addr;
        BOOL ret_val= TRUE;

        flash_addr= page_index << 9;

        // enable flash (NCS = 0)
        reg_value= 0;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_EN_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH_EN write failed !\n");
                return FALSE;
        }

        // write opcode
        reg_value= CVT_V1724_FOP_PAGE_PROG_TH_BUF1;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                ret_val= FALSE;
                goto exit_point;
        }
        // write address
        reg_value= (unsigned char)( flash_addr>> 16);
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                ret_val= FALSE;
                goto exit_point;
        }
        reg_value= (unsigned char)( flash_addr>> 8);
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                ret_val= FALSE;
                goto exit_point;
        }
        reg_value= (unsigned char) flash_addr;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                ret_val= FALSE;
                goto exit_point;
        }
        // write flash page
        for (i= 0; i< V1724_FLASH_PAGE_SIZE; i++)
        {
                reg_value= page_buff[ i];
                if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
                {
                        TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                        ret_val= FALSE;
                        goto exit_point;
                }
        }

exit_point:
        // disable flash (NCS = 1)
        reg_value= 1;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_EN_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH_EN write failed !\n");
                ret_val= FALSE;
        }

        // wait 50ms
        delay( 50);
        return ret_val;
}

//
BOOL cvt_V1724_read_flash_page( cvt_V1724_data* p_data, UINT8* page_buff, UINT32 page_index)
{
        int i;
        UINT16 reg_value;
        UINT32 flash_addr;
        BOOL ret_val= TRUE;

        flash_addr= page_index<< 9;

        // enable flash (NCS = 0)
        reg_value= 0;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_EN_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH_EN write failed !\n");
                return FALSE;
        }

        // write opcode
        reg_value= CVT_V1724_FOP_PAGE_READ;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                ret_val= FALSE;
                goto exit_point;
        }
        // write address
        reg_value= (unsigned char)( flash_addr>> 16);
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                ret_val= FALSE;
                goto exit_point;
        }
        reg_value= (unsigned char)( flash_addr>> 8);
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                ret_val= FALSE;
                goto exit_point;
        }
        reg_value= (unsigned char) flash_addr;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                ret_val= FALSE;
                goto exit_point;
        }


        // additional don't care bytes
        for (i=0; i<4; i++)
        {
                reg_value= 0;
                if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
                {
                        TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                        ret_val= FALSE;
                        goto exit_point;
                }
        }

        // read flash page
        for (i= 0; i< V1724_FLASH_PAGE_SIZE; i++)
        {
                if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
                {
                        TRACE( "V1724 CVT_V1724_FLASH read failed !\n");
                        ret_val= FALSE;
                        goto exit_point;
                }
                page_buff[ i]= ( UINT8)reg_value;
        }

exit_point:
        // disable flash (NCS = 1)
        reg_value= 1;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_EN_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH_EN write failed !\n");
                ret_val= FALSE;
        }

        return ret_val;
}

//
BOOL cvt_V1724_erase_flash_page( cvt_V1724_data* p_data, UINT32 page_index)
{
        UINT16 reg_value;
        UINT32 flash_addr;
        BOOL ret_val= TRUE;

        flash_addr= page_index<< 9;

        // enable flash (NCS = 0)
        reg_value= 0;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_EN_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH_EN write failed !\n");
                return FALSE;
        }

        // write opcode
        reg_value= CVT_V1724_FOP_PAGE_ERASE;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                ret_val= FALSE;
                goto exit_point;
        }
        // write address
        reg_value= (unsigned char)( flash_addr>> 16);
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                ret_val= FALSE;
                goto exit_point;
        }
        reg_value= (unsigned char)( flash_addr>> 8);
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                ret_val= FALSE;
                goto exit_point;
        }
        reg_value= (unsigned char) flash_addr;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                ret_val= FALSE;
                goto exit_point;
        }
exit_point:
        // disable flash (NCS = 1)
        reg_value= 1;
        if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_EN_INDEX, &reg_value))
        {
                TRACE( "V1724 CVT_V1724_FLASH_EN write failed !\n");
                ret_val= FALSE;
        }

        return ret_val;
}

//
BOOL cvt_V1724_fw_upgrade( cvt_V1724_data* p_data, const UINT8* data_buff, UINT32 data_size, CVT_V1724_FLASH_BANK flash_bank)
{

        UINT32 tot_bytes= 0;
        UINT8 tmp_page_w[ V1724_FLASH_PAGE_SIZE], tmp_page_r[ V1724_FLASH_PAGE_SIZE];

        switch( flash_bank)
        {
        case CVT_V1724_FB_STANDARD:             // Standard (boot) flash page
        case CVT_V1724_FB_BACKUP:               // Backup flash page
                break;
        default:
                TRACE( "V1724 cvt_V1724_fw_upgrade Invalid flash bank!\n");
                return FALSE;
        }

        // Swap bits into data bytes
        while( tot_bytes< data_size)
        {
                int i;
                // pepare temporary page to write
                for( i= 0; ( i< V1724_FLASH_PAGE_SIZE)&& ( tot_bytes< data_size); i++)
                {
                        // bitwise byte rotation
                        tmp_page_w[ i]= cvt_swap_bits( data_buff[ tot_bytes++]);
                }
                // write page to flash
                if( !cvt_V1724_write_flash_page( p_data, tmp_page_w, flash_bank))
                {
                        TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
                        return FALSE;
                }
                // read page from flash
                if( !cvt_V1724_read_flash_page( p_data, tmp_page_r, flash_bank))
                {
                        TRACE( "V1724 CVT_V1724_FLASH read failed !\n");
                        return FALSE;
                }
                // verify pages
                if( memcmp( tmp_page_r, tmp_page_w, V1724_FLASH_PAGE_SIZE))
                {
                        // read page differs from page written 
                        TRACE( "V1724 cvt_V1724_fw_upgrade page verify failure!\n");
                        return FALSE;
                }
                ++flash_bank;
        }

        return TRUE;
}

---