cvt_V1724.h

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#ifndef __CVT_V1724_DEF_H
#define __CVT_V1724_DEF_H

// File includes
#include "cvt_common_defs.h"
#include "cvt_board_commons.h"
// Global defines

#define CVT_V1724_THRESHOLD_NUM                 8                       



typedef struct
{
        cvt_board_data  m_common_data;                          
        //
        // Board specific data

        UINT32 *m_cache_sample_buffer;                          
        UINT32 m_cache_sample_buffer_size;                      
        UINT32 m_cache_sample_buffer_read_bytes;        
} cvt_V1724_data;

// Registers address
//
// Readout Buffer
#define CVT_V1724_OUT_BUFFER_ADD                                        0x0000                          
//
// Channel broadcast registers
#define CVT_V1724_BROAD_CH_CTRL_ADD                                     0x8000                          
#define CVT_V1724_BROAD_CH_SET_CTRL_ADD                         0x8004                          
#define CVT_V1724_BROAD_CH_CLEAR_CTRL_ADD                       0x8008                          
#define CVT_V1724_BROAD_CH_BUFF_SIZE_ADD                        0x800C                          
#define CVT_V1724_BROAD_CH_BUFF_FLUSH_ADD                       0x8010                          
#define CVT_V1724_BROAD_CH_RND_ACC_ADD                          0x8014                          
//
// VME registers
#define CVT_V1724_ACQ_CONTROL_ADD                                       0x8100                          
#define CVT_V1724_ACQ_STATUS_ADD                                        0x8104                          
#define CVT_V1724_SW_TRIGGER_ADD                                        0x8108                          
#define CVT_V1724_TRIGGER_SRC_ENABLE_ADD                        0x810C                          
#define CVT_V1724_FP_TRIGGER_OUT_ENABLE_ADD                     0x8110                          
#define CVT_V1724_POST_TRIG_ADD                                         0x8114                          
#define CVT_V1724_FRONT_PANEL_IO_ADD                            0x8118                          
#define CVT_V1724_FRONT_PANEL_IO_CTRL_ADD                       0x811C                          
#define CVT_V1724_CH_ENABLE_ADD                                         0x8120                          
#define CVT_V1724_FW_REV_ADD                                            0x8124                          
#define CVT_V1724_DOWNSAMPLE_FACT_ADD                           0x8128                          
#define CVT_V1724_EVENT_STORED_ADD                                      0x812C                          
#define CVT_V1724_VME_CONTROL_ADD                                       0xEF00                          
#define CVT_V1724_VME_STATUS_ADD                                        0xEF04                          
#define CVT_V1724_BOARD_ID_ADD                                          0xEF08                          
#define CVT_V1724_MCST_CBLT_ADD_CTRL_ADD                        0xEF0C                          
#define CVT_V1724_RELOCATION_ADDRESS_ADD                        0xEF10                          
#define CVT_V1724_INT_STATUS_ID_ADD                                     0xEF14                          
#define CVT_V1724_INT_EVENT_NUM_ADD                                     0xEF18                          
#define CVT_V1724_BLT_EVENT_NUM_ADD                                     0xEF1C                          
#define CVT_V1724_SCRATCH_ADD                                           0xEF20                          
#define CVT_V1724_SW_RESET_ADD                                          0xEF24                          
#define CVT_V1724_SW_CLEAR_ADD                                          0xEF28                          
#define CVT_V1724_FLASH_EN_ADD                                          0xEF2C                          
#define CVT_V1724_FLASH_DATA_ADD                                        0xEF30                          
#define CVT_V1724_RELOAD_CONFIG_ADD                                     0xEF34                          
#define CVT_V1724_BASE_ADDRESS_ADD                                      0xEF38                          
#define CVT_V1724_ROM_CHKSUM_ADD                                        0xF000                          
#define CVT_V1724_ROM_CHKSUM_LEN_2_ADD                          0xF004                          
#define CVT_V1724_ROM_CHKSUM_LEN_1_ADD                          0xF008                          
#define CVT_V1724_ROM_CHKSUM_LEN_0_ADD                          0xF00C                          
#define CVT_V1724_ROM_CONST_2_ADD                                       0xF010                          
#define CVT_V1724_ROM_CONST_1_ADD                                       0xF014                          
#define CVT_V1724_ROM_CONST_0_ADD                                       0xF018                          
#define CVT_V1724_ROM_C_CODE_ADD                                        0xF01C                          
#define CVT_V1724_ROM_R_CODE_ADD                                        0xF020                          
#define CVT_V1724_ROM_OUI_2_ADD                                         0xF024                          
#define CVT_V1724_ROM_OUI_1_ADD                                         0xF028                          
#define CVT_V1724_ROM_OUI_0_ADD                                         0xF02C                          
#define CVT_V1724_ROM_VERSION_ADD                                       0xF030                          
#define CVT_V1724_ROM_BOARD_ID_2_ADD                            0xF034                          
#define CVT_V1724_ROM_BOARD_ID_1_ADD                            0xF038                          
#define CVT_V1724_ROM_BOARD_ID_0_ADD                            0xF03C                          
#define CVT_V1724_ROM_REVISION_3_ADD                            0xF040                          
#define CVT_V1724_ROM_REVISION_2_ADD                            0xF044                          
#define CVT_V1724_ROM_REVISION_1_ADD                            0xF048                          
#define CVT_V1724_ROM_REVISION_0_ADD                            0xF04C                          
#define CVT_V1724_ROM_SERIAL_1_ADD                                      0xF080                          
#define CVT_V1724_ROM_SERIAL_0_ADD                                      0xF084                          
//
// CH 0
#define CVT_V1724_CH0_RESERVED_RND_ACC_ADD                      0x1014                          
#define CVT_V1724_CH0_THRESHOLD_ADD                                     0x1080                          
#define CVT_V1724_CH0_TIME_OVER_UNDER_THR_ADD           0x1084                          
#define CVT_V1724_CH0_STATUS_ADD                                        0x1088                          
#define CVT_V1724_CH0_FW_REV_ADD                                        0x108C                          
#define CVT_V1724_CH0_BUFF_OCCUPANCY_ADD                        0x1094                          
#define CVT_V1724_CH0_DAC_CONF_ADD                                      0x1098                          
#define CVT_V1724_CH0_ADC_CONF_ADD                                      0x109C                          
#define CVT_V1724_CH0_RESERVED_ADC_DEBUG_ADD            0x10A0                          
#define CVT_V1724_CH0_RESERVED_MEM_DATA_ADD                     0x10A4                          
#define CVT_V1724_CH0_RESERVED_MEM_ADDRESS_ADD          0x10A8                          
//
// CH 1
#define CVT_V1724_CH1_RESERVED_RND_ACC_ADD                      0x1114                          
#define CVT_V1724_CH1_THRESHOLD_ADD                                     0x1180                          
#define CVT_V1724_CH1_TIME_OVER_UNDER_THR_ADD           0x1184                          
#define CVT_V1724_CH1_STATUS_ADD                                        0x1188                          
#define CVT_V1724_CH1_FW_REV_ADD                                        0x118C                          
#define CVT_V1724_CH1_BUFF_OCCUPANCY_ADD                        0x1194                          
#define CVT_V1724_CH1_DAC_CONF_ADD                                      0x1198                          
#define CVT_V1724_CH1_ADC_CONF_ADD                                      0x119C                          
#define CVT_V1724_CH1_RESERVED_ADC_DEBUG_ADD            0x11A0                          
#define CVT_V1724_CH1_RESERVED_MEM_DATA_ADD                     0x11A4                          
#define CVT_V1724_CH1_RESERVED_MEM_ADDRESS_ADD          0x11A8                          
//
// CH 2
#define CVT_V1724_CH2_RESERVED_RND_ACC_ADD                      0x1214                          
#define CVT_V1724_CH2_THRESHOLD_ADD                                     0x1280                          
#define CVT_V1724_CH2_TIME_OVER_UNDER_THR_ADD           0x1284                          
#define CVT_V1724_CH2_STATUS_ADD                                        0x1288                          
#define CVT_V1724_CH2_FW_REV_ADD                                        0x128C                          
#define CVT_V1724_CH2_BUFF_OCCUPANCY_ADD                        0x1294                          
#define CVT_V1724_CH2_DAC_CONF_ADD                                      0x1298                          
#define CVT_V1724_CH2_ADC_CONF_ADD                                      0x129C                          
#define CVT_V1724_CH2_RESERVED_ADC_DEBUG_ADD            0x12A0                          
#define CVT_V1724_CH2_RESERVED_MEM_DATA_ADD                     0x12A4                          
#define CVT_V1724_CH2_RESERVED_MEM_ADDRESS_ADD          0x12A8                          
//
// CH 3
#define CVT_V1724_CH3_RESERVED_RND_ACC_ADD                      0x1314                          
#define CVT_V1724_CH3_THRESHOLD_ADD                                     0x1380                          
#define CVT_V1724_CH3_TIME_OVER_UNDER_THR_ADD           0x1384                          
#define CVT_V1724_CH3_STATUS_ADD                                        0x1388                          
#define CVT_V1724_CH3_FW_REV_ADD                                        0x138C                          
#define CVT_V1724_CH3_BUFF_OCCUPANCY_ADD                        0x1394                          
#define CVT_V1724_CH3_DAC_CONF_ADD                                      0x1398                          
#define CVT_V1724_CH3_ADC_CONF_ADD                                      0x139C                          
#define CVT_V1724_CH3_RESERVED_ADC_DEBUG_ADD            0x13A0                          
#define CVT_V1724_CH3_RESERVED_MEM_DATA_ADD                     0x13A4                          
#define CVT_V1724_CH3_RESERVED_MEM_ADDRESS_ADD          0x13A8                          
//
// CH 4
#define CVT_V1724_CH4_RESERVED_RND_ACC_ADD                      0x1414                          
#define CVT_V1724_CH4_THRESHOLD_ADD                                     0x1480                          
#define CVT_V1724_CH4_TIME_OVER_UNDER_THR_ADD           0x1484                          
#define CVT_V1724_CH4_STATUS_ADD                                        0x1488                          
#define CVT_V1724_CH4_FW_REV_ADD                                        0x148C                          
#define CVT_V1724_CH4_BUFF_OCCUPANCY_ADD                        0x1494                          
#define CVT_V1724_CH4_DAC_CONF_ADD                                      0x1498                          
#define CVT_V1724_CH4_ADC_CONF_ADD                                      0x149C                          
#define CVT_V1724_CH4_RESERVED_ADC_DEBUG_ADD            0x14A0                          
#define CVT_V1724_CH4_RESERVED_MEM_DATA_ADD                     0x14A4                          
#define CVT_V1724_CH4_RESERVED_MEM_ADDRESS_ADD          0x14A8                          
//
// CH 5
#define CVT_V1724_CH5_RESERVED_RND_ACC_ADD                      0x1514                          
#define CVT_V1724_CH5_THRESHOLD_ADD                                     0x1580                          
#define CVT_V1724_CH5_TIME_OVER_UNDER_THR_ADD           0x1584                          
#define CVT_V1724_CH5_STATUS_ADD                                        0x1588                          
#define CVT_V1724_CH5_FW_REV_ADD                                        0x158C                          
#define CVT_V1724_CH5_BUFF_OCCUPANCY_ADD                        0x1594                          
#define CVT_V1724_CH5_DAC_CONF_ADD                                      0x1598                          
#define CVT_V1724_CH5_ADC_CONF_ADD                                      0x159C                          
#define CVT_V1724_CH5_RESERVED_ADC_DEBUG_ADD            0x15A0                          
#define CVT_V1724_CH5_RESERVED_MEM_DATA_ADD                     0x15A4                          
#define CVT_V1724_CH5_RESERVED_MEM_ADDRESS_ADD          0x15A8                          
//
// CH 6
#define CVT_V1724_CH6_RESERVED_RND_ACC_ADD                      0x1614                          
#define CVT_V1724_CH6_THRESHOLD_ADD                                     0x1680                          
#define CVT_V1724_CH6_TIME_OVER_UNDER_THR_ADD           0x1684                          
#define CVT_V1724_CH6_STATUS_ADD                                        0x1688                          
#define CVT_V1724_CH6_FW_REV_ADD                                        0x168C                          
#define CVT_V1724_CH6_BUFF_OCCUPANCY_ADD                        0x1694                          
#define CVT_V1724_CH6_DAC_CONF_ADD                                      0x1698                          
#define CVT_V1724_CH6_ADC_CONF_ADD                                      0x169C                          
#define CVT_V1724_CH6_RESERVED_ADC_DEBUG_ADD            0x16A0                          
#define CVT_V1724_CH6_RESERVED_MEM_DATA_ADD                     0x16A4                          
#define CVT_V1724_CH6_RESERVED_MEM_ADDRESS_ADD          0x16A8                          
//
// CH 7
#define CVT_V1724_CH7_RESERVED_RND_ACC_ADD                      0x1714                          
#define CVT_V1724_CH7_THRESHOLD_ADD                                     0x1780                          
#define CVT_V1724_CH7_TIME_OVER_UNDER_THR_ADD           0x1784                          
#define CVT_V1724_CH7_STATUS_ADD                                        0x1788                          
#define CVT_V1724_CH7_FW_REV_ADD                                        0x178C                          
#define CVT_V1724_CH7_BUFF_OCCUPANCY_ADD                        0x1794                          
#define CVT_V1724_CH7_DAC_CONF_ADD                                      0x1798                          
#define CVT_V1724_CH7_ADC_CONF_ADD                                      0x179C                          
#define CVT_V1724_CH7_RESERVED_ADC_DEBUG_ADD            0x17A0                          
#define CVT_V1724_CH7_RESERVED_MEM_DATA_ADD                     0x17A4                          
#define CVT_V1724_CH7_RESERVED_MEM_ADDRESS_ADD          0x17A8                          

// Registers data size

//
// Readout Buffer
#define CVT_V1724_OUT_BUFFER_DATA_SIZE                          cvD64                           
// #define CVT_V1724_OUT_BUFFER_DATA_SIZE                               cvD32                           
//
// Channel broadcast registers
#define CVT_V1724_BROAD_CH_CTRL_DATA_SIZE                       cvD32                           
#define CVT_V1724_BROAD_CH_SET_CTRL_DATA_SIZE           cvD32                           
#define CVT_V1724_BROAD_CH_CLEAR_CTRL_DATA_SIZE         cvD32                           
#define CVT_V1724_BROAD_CH_BUFF_SIZE_DATA_SIZE          cvD32                           
#define CVT_V1724_BROAD_CH_BUFF_FLUSH_DATA_SIZE         cvD32                           
#define CVT_V1724_BROAD_CH_RND_ACC_DATA_SIZE            cvD32                           
//
// VME registers
#define CVT_V1724_ACQ_CONTROL_DATA_SIZE                         cvD32                           
#define CVT_V1724_ACQ_STATUS_DATA_SIZE                          cvD32                           
#define CVT_V1724_SW_TRIGGER_DATA_SIZE                          cvD32                           
#define CVT_V1724_TRIGGER_SRC_ENABLE_DATA_SIZE          cvD32                           
#define CVT_V1724_FP_TRIGGER_OUT_ENABLE_DATA_SIZE       cvD32                           
#define CVT_V1724_POST_TRIG_DATA_SIZE                           cvD32                           
#define CVT_V1724_FRONT_PANEL_IO_DATA_SIZE                      cvD32                           
#define CVT_V1724_FRONT_PANEL_IO_CTRL_DATA_SIZE         cvD32                           
#define CVT_V1724_CH_ENABLE_DATA_SIZE                           cvD32                           
#define CVT_V1724_FW_REV_DATA_SIZE                                      cvD32                           
#define CVT_V1724_DOWNSAMPLE_FACT_DATA_SIZE                     cvD32                           
#define CVT_V1724_EVENT_STORED_DATA_SIZE                        cvD32                           
#define CVT_V1724_VME_CONTROL_DATA_SIZE                         cvD32                           
#define CVT_V1724_VME_STATUS_DATA_SIZE                          cvD32                           
#define CVT_V1724_BOARD_ID_DATA_SIZE                            cvD32                           
#define CVT_V1724_MCST_CBLT_ADD_CTRL_DATA_SIZE          cvD32                           
#define CVT_V1724_RELOCATION_ADDRESS_DATA_SIZE          cvD32                           
#define CVT_V1724_INT_STATUS_ID_DATA_SIZE                       cvD32                           
#define CVT_V1724_INT_EVENT_NUM_DATA_SIZE                       cvD32                           
#define CVT_V1724_BLT_EVENT_NUM_DATA_SIZE                       cvD32                           
#define CVT_V1724_SCRATCH_DATA_SIZE                                     cvD32                           
#define CVT_V1724_SW_RESET_DATA_SIZE                            cvD32                           
#define CVT_V1724_SW_CLEAR_DATA_SIZE                            cvD32                           
#define CVT_V1724_FLASH_EN_DATA_SIZE                            cvD32                           
#define CVT_V1724_FLASH_DATA_DATA_SIZE                          cvD32                           
#define CVT_V1724_RELOAD_CONFIG_DATA_SIZE                       cvD32                           
#define CVT_V1724_BASE_ADDRESS_DATA_SIZE                        cvD32                           
#define CVT_V1724_ROM_CHKSUM_DATA_SIZE                          cvD32                           
#define CVT_V1724_ROM_CHKSUM_LEN_2_DATA_SIZE            cvD32                           
#define CVT_V1724_ROM_CHKSUM_LEN_1_DATA_SIZE            cvD32                           
#define CVT_V1724_ROM_CHKSUM_LEN_0_DATA_SIZE            cvD32                           
#define CVT_V1724_ROM_CONST_2_DATA_SIZE                         cvD32                           
#define CVT_V1724_ROM_CONST_1_DATA_SIZE                         cvD32                           
#define CVT_V1724_ROM_CONST_0_DATA_SIZE                         cvD32                           
#define CVT_V1724_ROM_C_CODE_DATA_SIZE                          cvD32                           
#define CVT_V1724_ROM_R_CODE_DATA_SIZE                          cvD32                           
#define CVT_V1724_ROM_OUI_2_DATA_SIZE                           cvD32                           
#define CVT_V1724_ROM_OUI_1_DATA_SIZE                           cvD32                           
#define CVT_V1724_ROM_OUI_0_DATA_SIZE                           cvD32                           
#define CVT_V1724_ROM_VERSION_DATA_SIZE                         cvD32                           
#define CVT_V1724_ROM_BOARD_ID_2_DATA_SIZE                      cvD32                           
#define CVT_V1724_ROM_BOARD_ID_1_DATA_SIZE                      cvD32                           
#define CVT_V1724_ROM_BOARD_ID_0_DATA_SIZE                      cvD32                           
#define CVT_V1724_ROM_REVISION_3_DATA_SIZE                      cvD32                           
#define CVT_V1724_ROM_REVISION_2_DATA_SIZE                      cvD32                           
#define CVT_V1724_ROM_REVISION_1_DATA_SIZE                      cvD32                           
#define CVT_V1724_ROM_REVISION_0_DATA_SIZE                      cvD32                           
#define CVT_V1724_ROM_SERIAL_1_DATA_SIZE                        cvD32                           
#define CVT_V1724_ROM_SERIAL_0_DATA_SIZE                        cvD32                           
//
// CH 0
#define CVT_V1724_CH0_RESERVED_RND_ACC_DATA_SIZE                cvD32                           
#define CVT_V1724_CH0_THRESHOLD_DATA_SIZE                               cvD32                           
#define CVT_V1724_CH0_TIME_OVER_UNDER_THR_DATA_SIZE             cvD32                           
#define CVT_V1724_CH0_STATUS_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH0_FW_REV_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH0_BUFF_OCCUPANCY_DATA_SIZE                  cvD32                           
#define CVT_V1724_CH0_DAC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH0_ADC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH0_RESERVED_ADC_DEBUG_DATA_SIZE              cvD32                           
#define CVT_V1724_CH0_RESERVED_MEM_DATA_DATA_SIZE               cvD32                           
#define CVT_V1724_CH0_RESERVED_MEM_ADDRESS_DATA_SIZE    cvD32                           
//
// CH 1
#define CVT_V1724_CH1_RESERVED_RND_ACC_DATA_SIZE                cvD32                           
#define CVT_V1724_CH1_THRESHOLD_DATA_SIZE                               cvD32                           
#define CVT_V1724_CH1_TIME_OVER_UNDER_THR_DATA_SIZE             cvD32                           
#define CVT_V1724_CH1_STATUS_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH1_FW_REV_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH1_BUFF_OCCUPANCY_DATA_SIZE                  cvD32                           
#define CVT_V1724_CH1_DAC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH1_ADC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH1_RESERVED_ADC_DEBUG_DATA_SIZE              cvD32                           
#define CVT_V1724_CH1_RESERVED_MEM_DATA_DATA_SIZE               cvD32                           
#define CVT_V1724_CH1_RESERVED_MEM_ADDRESS_DATA_SIZE    cvD32                           
//
// CH 2
#define CVT_V1724_CH2_RESERVED_RND_ACC_DATA_SIZE                cvD32                           
#define CVT_V1724_CH2_THRESHOLD_DATA_SIZE                               cvD32                           
#define CVT_V1724_CH2_TIME_OVER_UNDER_THR_DATA_SIZE             cvD32                           
#define CVT_V1724_CH2_STATUS_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH2_FW_REV_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH2_BUFF_OCCUPANCY_DATA_SIZE                  cvD32                           
#define CVT_V1724_CH2_DAC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH2_ADC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH2_RESERVED_ADC_DEBUG_DATA_SIZE              cvD32                           
#define CVT_V1724_CH2_RESERVED_MEM_DATA_DATA_SIZE               cvD32                           
#define CVT_V1724_CH2_RESERVED_MEM_ADDRESS_DATA_SIZE    cvD32                           
//
// CH 3
#define CVT_V1724_CH3_RESERVED_RND_ACC_DATA_SIZE                cvD32                           
#define CVT_V1724_CH3_THRESHOLD_DATA_SIZE                               cvD32                           
#define CVT_V1724_CH3_TIME_OVER_UNDER_THR_DATA_SIZE             cvD32                           
#define CVT_V1724_CH3_STATUS_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH3_FW_REV_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH3_BUFF_OCCUPANCY_DATA_SIZE                  cvD32                           
#define CVT_V1724_CH3_DAC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH3_ADC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH3_RESERVED_ADC_DEBUG_DATA_SIZE              cvD32                           
#define CVT_V1724_CH3_RESERVED_MEM_DATA_DATA_SIZE               cvD32                           
#define CVT_V1724_CH3_RESERVED_MEM_ADDRESS_DATA_SIZE    cvD32                           
//
// CH 4
#define CVT_V1724_CH4_RESERVED_RND_ACC_DATA_SIZE                cvD32                           
#define CVT_V1724_CH4_THRESHOLD_DATA_SIZE                               cvD32                           
#define CVT_V1724_CH4_TIME_OVER_UNDER_THR_DATA_SIZE             cvD32                           
#define CVT_V1724_CH4_STATUS_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH4_FW_REV_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH4_BUFF_OCCUPANCY_DATA_SIZE                  cvD32                           
#define CVT_V1724_CH4_DAC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH4_ADC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH4_RESERVED_ADC_DEBUG_DATA_SIZE              cvD32                           
#define CVT_V1724_CH4_RESERVED_MEM_DATA_DATA_SIZE               cvD32                           
#define CVT_V1724_CH4_RESERVED_MEM_ADDRESS_DATA_SIZE    cvD32                           
//
// CH 5
#define CVT_V1724_CH5_RESERVED_RND_ACC_DATA_SIZE                cvD32                           
#define CVT_V1724_CH5_THRESHOLD_DATA_SIZE                               cvD32                           
#define CVT_V1724_CH5_TIME_OVER_UNDER_THR_DATA_SIZE             cvD32                           
#define CVT_V1724_CH5_STATUS_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH5_FW_REV_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH5_BUFF_OCCUPANCY_DATA_SIZE                  cvD32                           
#define CVT_V1724_CH5_DAC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH5_ADC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH5_RESERVED_ADC_DEBUG_DATA_SIZE              cvD32                           
#define CVT_V1724_CH5_RESERVED_MEM_DATA_DATA_SIZE               cvD32                           
#define CVT_V1724_CH5_RESERVED_MEM_ADDRESS_DATA_SIZE    cvD32                           
//
// CH 6
#define CVT_V1724_CH6_RESERVED_RND_ACC_DATA_SIZE                cvD32                           
#define CVT_V1724_CH6_THRESHOLD_DATA_SIZE                               cvD32                           
#define CVT_V1724_CH6_TIME_OVER_UNDER_THR_DATA_SIZE             cvD32                           
#define CVT_V1724_CH6_STATUS_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH6_FW_REV_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH6_BUFF_OCCUPANCY_DATA_SIZE                  cvD32                           
#define CVT_V1724_CH6_DAC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH6_ADC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH6_RESERVED_ADC_DEBUG_DATA_SIZE              cvD32                           
#define CVT_V1724_CH6_RESERVED_MEM_DATA_DATA_SIZE               cvD32                           
#define CVT_V1724_CH6_RESERVED_MEM_ADDRESS_DATA_SIZE    cvD32                           
//
// CH 7
#define CVT_V1724_CH7_RESERVED_RND_ACC_DATA_SIZE                cvD32                           
#define CVT_V1724_CH7_THRESHOLD_DATA_SIZE                               cvD32                           
#define CVT_V1724_CH7_TIME_OVER_UNDER_THR_DATA_SIZE             cvD32                           
#define CVT_V1724_CH7_STATUS_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH7_FW_REV_DATA_SIZE                                  cvD32                           
#define CVT_V1724_CH7_BUFF_OCCUPANCY_DATA_SIZE                  cvD32                           
#define CVT_V1724_CH7_DAC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH7_ADC_CONF_DATA_SIZE                                cvD32                           
#define CVT_V1724_CH7_RESERVED_ADC_DEBUG_DATA_SIZE              cvD32                           
#define CVT_V1724_CH7_RESERVED_MEM_DATA_DATA_SIZE               cvD32                           
#define CVT_V1724_CH7_RESERVED_MEM_ADDRESS_DATA_SIZE    cvD32                           

// Registers address modifiers

//
// Readout Buffer
#define CVT_V1724_OUT_BUFFER_AM                                         cvA32_S_MBLT                            
// #define CVT_V1724_OUT_BUFFER_AM                                              cvA32_U_BLT                             
//
// Channel broadcast registers
#define CVT_V1724_BROAD_CH_CTRL_AM                                      cvA32_S_DATA                            
#define CVT_V1724_BROAD_CH_SET_CTRL_AM                          cvA32_S_DATA                            
#define CVT_V1724_BROAD_CH_CLEAR_CTRL_AM                        cvA32_S_DATA                            
#define CVT_V1724_BROAD_CH_BUFF_SIZE_AM                         cvA32_S_DATA                            
#define CVT_V1724_BROAD_CH_BUFF_FLUSH_AM                        cvA32_S_DATA                            
#define CVT_V1724_BROAD_CH_RND_ACC_AM                           cvA32_S_DATA                            
//
// VME registers
#define CVT_V1724_ACQ_CONTROL_AM                                        cvA32_S_DATA                            
#define CVT_V1724_ACQ_STATUS_AM                                         cvA32_S_DATA                            
#define CVT_V1724_SW_TRIGGER_AM                                         cvA32_S_DATA                            
#define CVT_V1724_TRIGGER_SRC_ENABLE_AM                         cvA32_S_DATA                            
#define CVT_V1724_FP_TRIGGER_OUT_ENABLE_AM                      cvA32_S_DATA                            
#define CVT_V1724_POST_TRIG_AM                                          cvA32_S_DATA                            
#define CVT_V1724_FRONT_PANEL_IO_AM                                     cvA32_S_DATA                            
#define CVT_V1724_FRONT_PANEL_IO_CTRL_AM                        cvA32_S_DATA                            
#define CVT_V1724_CH_ENABLE_AM                                          cvA32_S_DATA                            
#define CVT_V1724_FW_REV_AM                                                     cvA32_S_DATA                            
#define CVT_V1724_DOWNSAMPLE_FACT_AM                            cvA32_S_DATA                            
#define CVT_V1724_EVENT_STORED_AM                                       cvA32_S_DATA                            
#define CVT_V1724_VME_CONTROL_AM                                        cvA32_S_DATA                            
#define CVT_V1724_VME_STATUS_AM                                         cvA32_S_DATA                            
#define CVT_V1724_BOARD_ID_AM                                           cvA32_S_DATA                            
#define CVT_V1724_MCST_CBLT_ADD_CTRL_AM                         cvA32_S_DATA                            
#define CVT_V1724_RELOCATION_ADDRESS_AM                         cvA32_S_DATA                            
#define CVT_V1724_INT_STATUS_ID_AM                                      cvA32_S_DATA                            
#define CVT_V1724_INT_EVENT_NUM_AM                                      cvA32_S_DATA                            
#define CVT_V1724_BLT_EVENT_NUM_AM                                      cvA32_S_DATA                            
#define CVT_V1724_SCRATCH_AM                                            cvA32_S_DATA                            
#define CVT_V1724_SW_RESET_AM                                           cvA32_S_DATA                            
#define CVT_V1724_SW_CLEAR_AM                                           cvA32_S_DATA                            
#define CVT_V1724_FLASH_EN_AM                                           cvA32_S_DATA                            
#define CVT_V1724_FLASH_DATA_AM                                         cvA32_S_DATA                            
#define CVT_V1724_RELOAD_CONFIG_AM                                      cvA32_S_DATA                            
#define CVT_V1724_BASE_ADDRESS_AM                                       cvA32_S_DATA                            
#define CVT_V1724_ROM_CHKSUM_AM                                         cvA32_S_DATA                            
#define CVT_V1724_ROM_CHKSUM_LEN_2_AM                           cvA32_S_DATA                            
#define CVT_V1724_ROM_CHKSUM_LEN_1_AM                           cvA32_S_DATA                            
#define CVT_V1724_ROM_CHKSUM_LEN_0_AM                           cvA32_S_DATA                            
#define CVT_V1724_ROM_CONST_2_AM                                        cvA32_S_DATA                            
#define CVT_V1724_ROM_CONST_1_AM                                        cvA32_S_DATA                            
#define CVT_V1724_ROM_CONST_0_AM                                        cvA32_S_DATA                            
#define CVT_V1724_ROM_C_CODE_AM                                         cvA32_S_DATA                            
#define CVT_V1724_ROM_R_CODE_AM                                         cvA32_S_DATA                            
#define CVT_V1724_ROM_OUI_2_AM                                          cvA32_S_DATA                            
#define CVT_V1724_ROM_OUI_1_AM                                          cvA32_S_DATA                            
#define CVT_V1724_ROM_OUI_0_AM                                          cvA32_S_DATA                            
#define CVT_V1724_ROM_VERSION_AM                                        cvA32_S_DATA                            
#define CVT_V1724_ROM_BOARD_ID_2_AM                                     cvA32_S_DATA                            
#define CVT_V1724_ROM_BOARD_ID_1_AM                                     cvA32_S_DATA                            
#define CVT_V1724_ROM_BOARD_ID_0_AM                                     cvA32_S_DATA                            
#define CVT_V1724_ROM_REVISION_3_AM                                     cvA32_S_DATA                            
#define CVT_V1724_ROM_REVISION_2_AM                                     cvA32_S_DATA                            
#define CVT_V1724_ROM_REVISION_1_AM                                     cvA32_S_DATA                            
#define CVT_V1724_ROM_REVISION_0_AM                                     cvA32_S_DATA                            
#define CVT_V1724_ROM_SERIAL_1_AM                                       cvA32_S_DATA                            
#define CVT_V1724_ROM_SERIAL_0_AM                                       cvA32_S_DATA                            
//
// CH 0
#define CVT_V1724_CH0_RESERVED_RND_ACC_AM                       cvA32_S_DATA                            
#define CVT_V1724_CH0_THRESHOLD_AM                                      cvA32_S_DATA                            
#define CVT_V1724_CH0_TIME_OVER_UNDER_THR_AM            cvA32_S_DATA                            
#define CVT_V1724_CH0_STATUS_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH0_FW_REV_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH0_BUFF_OCCUPANCY_AM                         cvA32_S_DATA                            
#define CVT_V1724_CH0_DAC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH0_ADC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH0_RESERVED_ADC_DEBUG_AM                     cvA32_S_DATA                            
#define CVT_V1724_CH0_RESERVED_MEM_DATA_AM                      cvA32_S_DATA                            
#define CVT_V1724_CH0_RESERVED_MEM_ADDRESS_AM           cvA32_S_DATA                            
//
// CH 1
#define CVT_V1724_CH1_RESERVED_RND_ACC_AM                       cvA32_S_DATA                            
#define CVT_V1724_CH1_THRESHOLD_AM                                      cvA32_S_DATA                            
#define CVT_V1724_CH1_TIME_OVER_UNDER_THR_AM            cvA32_S_DATA                            
#define CVT_V1724_CH1_STATUS_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH1_FW_REV_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH1_BUFF_OCCUPANCY_AM                         cvA32_S_DATA                            
#define CVT_V1724_CH1_DAC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH1_ADC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH1_RESERVED_ADC_DEBUG_AM                     cvA32_S_DATA                            
#define CVT_V1724_CH1_RESERVED_MEM_DATA_AM                      cvA32_S_DATA                            
#define CVT_V1724_CH1_RESERVED_MEM_ADDRESS_AM           cvA32_S_DATA                            
//
// CH 2
#define CVT_V1724_CH2_RESERVED_RND_ACC_AM                       cvA32_S_DATA                            
#define CVT_V1724_CH2_THRESHOLD_AM                                      cvA32_S_DATA                            
#define CVT_V1724_CH2_TIME_OVER_UNDER_THR_AM            cvA32_S_DATA                            
#define CVT_V1724_CH2_STATUS_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH2_FW_REV_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH2_BUFF_OCCUPANCY_AM                         cvA32_S_DATA                            
#define CVT_V1724_CH2_DAC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH2_ADC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH2_RESERVED_ADC_DEBUG_AM                     cvA32_S_DATA                            
#define CVT_V1724_CH2_RESERVED_MEM_DATA_AM                      cvA32_S_DATA                            
#define CVT_V1724_CH2_RESERVED_MEM_ADDRESS_AM           cvA32_S_DATA                            
//
// CH 3
#define CVT_V1724_CH3_RESERVED_RND_ACC_AM                       cvA32_S_DATA                            
#define CVT_V1724_CH3_THRESHOLD_AM                                      cvA32_S_DATA                            
#define CVT_V1724_CH3_TIME_OVER_UNDER_THR_AM            cvA32_S_DATA                            
#define CVT_V1724_CH3_STATUS_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH3_FW_REV_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH3_BUFF_OCCUPANCY_AM                         cvA32_S_DATA                            
#define CVT_V1724_CH3_DAC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH3_ADC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH3_RESERVED_ADC_DEBUG_AM                     cvA32_S_DATA                            
#define CVT_V1724_CH3_RESERVED_MEM_DATA_AM                      cvA32_S_DATA                            
#define CVT_V1724_CH3_RESERVED_MEM_ADDRESS_AM           cvA32_S_DATA                            
//
// CH 4
#define CVT_V1724_CH4_RESERVED_RND_ACC_AM                       cvA32_S_DATA                            
#define CVT_V1724_CH4_THRESHOLD_AM                                      cvA32_S_DATA                            
#define CVT_V1724_CH4_TIME_OVER_UNDER_THR_AM            cvA32_S_DATA                            
#define CVT_V1724_CH4_STATUS_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH4_FW_REV_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH4_BUFF_OCCUPANCY_AM                         cvA32_S_DATA                            
#define CVT_V1724_CH4_DAC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH4_ADC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH4_RESERVED_ADC_DEBUG_AM                     cvA32_S_DATA                            
#define CVT_V1724_CH4_RESERVED_MEM_DATA_AM                      cvA32_S_DATA                            
#define CVT_V1724_CH4_RESERVED_MEM_ADDRESS_AM           cvA32_S_DATA                            
//
// CH 5
#define CVT_V1724_CH5_RESERVED_RND_ACC_AM                       cvA32_S_DATA                            
#define CVT_V1724_CH5_THRESHOLD_AM                                      cvA32_S_DATA                            
#define CVT_V1724_CH5_TIME_OVER_UNDER_THR_AM            cvA32_S_DATA                            
#define CVT_V1724_CH5_STATUS_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH5_FW_REV_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH5_BUFF_OCCUPANCY_AM                         cvA32_S_DATA                            
#define CVT_V1724_CH5_DAC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH5_ADC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH5_RESERVED_ADC_DEBUG_AM                     cvA32_S_DATA                            
#define CVT_V1724_CH5_RESERVED_MEM_DATA_AM                      cvA32_S_DATA                            
#define CVT_V1724_CH5_RESERVED_MEM_ADDRESS_AM           cvA32_S_DATA                            
//
// CH 6
#define CVT_V1724_CH6_RESERVED_RND_ACC_AM                       cvA32_S_DATA                            
#define CVT_V1724_CH6_THRESHOLD_AM                                      cvA32_S_DATA                            
#define CVT_V1724_CH6_TIME_OVER_UNDER_THR_AM            cvA32_S_DATA                            
#define CVT_V1724_CH6_STATUS_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH6_FW_REV_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH6_BUFF_OCCUPANCY_AM                         cvA32_S_DATA                            
#define CVT_V1724_CH6_DAC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH6_ADC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH6_RESERVED_ADC_DEBUG_AM                     cvA32_S_DATA                            
#define CVT_V1724_CH6_RESERVED_MEM_DATA_AM                      cvA32_S_DATA                            
#define CVT_V1724_CH6_RESERVED_MEM_ADDRESS_AM           cvA32_S_DATA                            
//
// CH 7
#define CVT_V1724_CH7_RESERVED_RND_ACC_AM                       cvA32_S_DATA                            
#define CVT_V1724_CH7_THRESHOLD_AM                                      cvA32_S_DATA                            
#define CVT_V1724_CH7_TIME_OVER_UNDER_THR_AM            cvA32_S_DATA                            
#define CVT_V1724_CH7_STATUS_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH7_FW_REV_AM                                         cvA32_S_DATA                            
#define CVT_V1724_CH7_BUFF_OCCUPANCY_AM                         cvA32_S_DATA                            
#define CVT_V1724_CH7_DAC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH7_ADC_CONF_AM                                       cvA32_S_DATA                            
#define CVT_V1724_CH7_RESERVED_ADC_DEBUG_AM                     cvA32_S_DATA                            
#define CVT_V1724_CH7_RESERVED_MEM_DATA_AM                      cvA32_S_DATA                            
#define CVT_V1724_CH7_RESERVED_MEM_ADDRESS_AM           cvA32_S_DATA                            

// Registers indexes




typedef enum
{
//
// Readout Buffer
        CVT_V1724_OUT_BUFFER_INDEX,                                             
//
// Channel broadcast registers
        CVT_V1724_BROAD_CH_CTRL_INDEX,                                  
        CVT_V1724_BROAD_CH_SET_CTRL_INDEX,                              
        CVT_V1724_BROAD_CH_CLEAR_CTRL_INDEX,                    
        CVT_V1724_BROAD_CH_BUFF_SIZE_INDEX,                             
        CVT_V1724_BROAD_CH_BUFF_FLUSH_INDEX,                    
        CVT_V1724_BROAD_CH_RND_ACC_INDEX,                               
//
// VME registers
        CVT_V1724_ACQ_CONTROL_INDEX,                                    
        CVT_V1724_ACQ_STATUS_INDEX,                                             
        CVT_V1724_SW_TRIGGER_INDEX,                                             
        CVT_V1724_TRIGGER_SRC_ENABLE_INDEX,                             
        CVT_V1724_FP_TRIGGER_OUT_ENABLE_INDEX,                  
        CVT_V1724_POST_TRIG_INDEX,                                              
        CVT_V1724_FRONT_PANEL_IO_INDEX,                                 
        CVT_V1724_FRONT_PANEL_IO_CTRL_INDEX,                    
        CVT_V1724_CH_ENABLE_INDEX,                                              
        CVT_V1724_FW_REV_INDEX,                                                 
        CVT_V1724_DOWNSAMPLE_FACT_INDEX,                                
        CVT_V1724_EVENT_STORED_INDEX,                                   
        CVT_V1724_VME_CONTROL_INDEX,                                    
        CVT_V1724_VME_STATUS_INDEX,                                             
        CVT_V1724_BOARD_ID_INDEX,                                               
        CVT_V1724_MCST_CBLT_ADD_CTRL_INDEX,                             
        CVT_V1724_RELOCATION_ADDRESS_INDEX,                             
        CVT_V1724_INT_STATUS_ID_INDEX,                                  
        CVT_V1724_INT_EVENT_NUM_INDEX,                                  
        CVT_V1724_BLT_EVENT_NUM_INDEX,                                  
        CVT_V1724_SCRATCH_INDEX,                                                
        CVT_V1724_SW_RESET_INDEX,                                               
        CVT_V1724_SW_CLEAR_INDEX,                                               
        CVT_V1724_FLASH_EN_INDEX,                                               
        CVT_V1724_FLASH_DATA_INDEX,                                             
        CVT_V1724_RELOAD_CONFIG_INDEX,                                  
        CVT_V1724_BASE_ADDRESS_INDEX,                                   
        CVT_V1724_ROM_CHKSUM_INDEX,                                             
        CVT_V1724_ROM_CHKSUM_LEN_2_INDEX,                               
        CVT_V1724_ROM_CHKSUM_LEN_1_INDEX,                               
        CVT_V1724_ROM_CHKSUM_LEN_0_INDEX,                               
        CVT_V1724_ROM_CONST_2_INDEX,                                    
        CVT_V1724_ROM_CONST_1_INDEX,                                    
        CVT_V1724_ROM_CONST_0_INDEX,                                    
        CVT_V1724_ROM_C_CODE_INDEX,                                             
        CVT_V1724_ROM_R_CODE_INDEX,                                             
        CVT_V1724_ROM_OUI_2_INDEX,                                              
        CVT_V1724_ROM_OUI_1_INDEX,                                              
        CVT_V1724_ROM_OUI_0_INDEX,                                              
        CVT_V1724_ROM_VERSION_INDEX,                                    
        CVT_V1724_ROM_BOARD_ID_2_INDEX,                                 
        CVT_V1724_ROM_BOARD_ID_1_INDEX,                                 
        CVT_V1724_ROM_BOARD_ID_0_INDEX,                                 
        CVT_V1724_ROM_REVISION_3_INDEX,                                 
        CVT_V1724_ROM_REVISION_2_INDEX,                                 
        CVT_V1724_ROM_REVISION_1_INDEX,                                 
        CVT_V1724_ROM_REVISION_0_INDEX,                                 
        CVT_V1724_ROM_SERIAL_1_INDEX,                                   
        CVT_V1724_ROM_SERIAL_0_INDEX,                                   
//
// CH 0
        CVT_V1724_CH0_RESERVED_RND_ACC_INDEX,                   
        CVT_V1724_CH0_THRESHOLD_INDEX,                                  
        CVT_V1724_CH0_TIME_OVER_UNDER_THR_INDEX,                
        CVT_V1724_CH0_STATUS_INDEX,                                             
        CVT_V1724_CH0_FW_REV_INDEX,                                             
        CVT_V1724_CH0_BUFF_OCCUPANCY_INDEX,                             
        CVT_V1724_CH0_DAC_CONF_INDEX,                                   
        CVT_V1724_CH0_ADC_CONF_INDEX,                                   
        CVT_V1724_CH0_RESERVED_ADC_DEBUG_INDEX,                 
        CVT_V1724_CH0_RESERVED_MEM_DATA_INDEX,                  
        CVT_V1724_CH0_RESERVED_MEM_ADDRESS_INDEX,               
//
// CH 1
        CVT_V1724_CH1_RESERVED_RND_ACC_INDEX,                   
        CVT_V1724_CH1_THRESHOLD_INDEX,                                  
        CVT_V1724_CH1_TIME_OVER_UNDER_THR_INDEX,                
        CVT_V1724_CH1_STATUS_INDEX,                                             
        CVT_V1724_CH1_FW_REV_INDEX,                                             
        CVT_V1724_CH1_BUFF_OCCUPANCY_INDEX,                             
        CVT_V1724_CH1_DAC_CONF_INDEX,                                   
        CVT_V1724_CH1_ADC_CONF_INDEX,                                   
        CVT_V1724_CH1_RESERVED_ADC_DEBUG_INDEX,                 
        CVT_V1724_CH1_RESERVED_MEM_DATA_INDEX,                  
        CVT_V1724_CH1_RESERVED_MEM_ADDRESS_INDEX,               
//
// CH 2
        CVT_V1724_CH2_RESERVED_RND_ACC_INDEX,                   
        CVT_V1724_CH2_THRESHOLD_INDEX,                                  
        CVT_V1724_CH2_TIME_OVER_UNDER_THR_INDEX,                
        CVT_V1724_CH2_STATUS_INDEX,                                             
        CVT_V1724_CH2_FW_REV_INDEX,                                             
        CVT_V1724_CH2_BUFF_OCCUPANCY_INDEX,                             
        CVT_V1724_CH2_DAC_CONF_INDEX,                                   
        CVT_V1724_CH2_ADC_CONF_INDEX,                                   
        CVT_V1724_CH2_RESERVED_ADC_DEBUG_INDEX,                 
        CVT_V1724_CH2_RESERVED_MEM_DATA_INDEX,                  
        CVT_V1724_CH2_RESERVED_MEM_ADDRESS_INDEX,               
//
// CH 3
        CVT_V1724_CH3_RESERVED_RND_ACC_INDEX,                   
        CVT_V1724_CH3_THRESHOLD_INDEX,                                  
        CVT_V1724_CH3_TIME_OVER_UNDER_THR_INDEX,                
        CVT_V1724_CH3_STATUS_INDEX,                                             
        CVT_V1724_CH3_FW_REV_INDEX,                                             
        CVT_V1724_CH3_BUFF_OCCUPANCY_INDEX,                             
        CVT_V1724_CH3_DAC_CONF_INDEX,                                   
        CVT_V1724_CH3_ADC_CONF_INDEX,                                   
        CVT_V1724_CH3_RESERVED_ADC_DEBUG_INDEX,                 
        CVT_V1724_CH3_RESERVED_MEM_DATA_INDEX,                  
        CVT_V1724_CH3_RESERVED_MEM_ADDRESS_INDEX,               
//
// CH 4
        CVT_V1724_CH4_RESERVED_RND_ACC_INDEX,                   
        CVT_V1724_CH4_THRESHOLD_INDEX,                                  
        CVT_V1724_CH4_TIME_OVER_UNDER_THR_INDEX,                
        CVT_V1724_CH4_STATUS_INDEX,                                             
        CVT_V1724_CH4_FW_REV_INDEX,                                             
        CVT_V1724_CH4_BUFF_OCCUPANCY_INDEX,                             
        CVT_V1724_CH4_DAC_CONF_INDEX,                                   
        CVT_V1724_CH4_ADC_CONF_INDEX,                                   
        CVT_V1724_CH4_RESERVED_ADC_DEBUG_INDEX,                 
        CVT_V1724_CH4_RESERVED_MEM_DATA_INDEX,                  
        CVT_V1724_CH4_RESERVED_MEM_ADDRESS_INDEX,               
//
// CH 5
        CVT_V1724_CH5_RESERVED_RND_ACC_INDEX,                   
        CVT_V1724_CH5_THRESHOLD_INDEX,                                  
        CVT_V1724_CH5_TIME_OVER_UNDER_THR_INDEX,                
        CVT_V1724_CH5_STATUS_INDEX,                                             
        CVT_V1724_CH5_FW_REV_INDEX,                                             
        CVT_V1724_CH5_BUFF_OCCUPANCY_INDEX,                             
        CVT_V1724_CH5_DAC_CONF_INDEX,                                   
        CVT_V1724_CH5_ADC_CONF_INDEX,                                   
        CVT_V1724_CH5_RESERVED_ADC_DEBUG_INDEX,                 
        CVT_V1724_CH5_RESERVED_MEM_DATA_INDEX,                  
        CVT_V1724_CH5_RESERVED_MEM_ADDRESS_INDEX,               
//
// CH 6
        CVT_V1724_CH6_RESERVED_RND_ACC_INDEX,                   
        CVT_V1724_CH6_THRESHOLD_INDEX,                                  
        CVT_V1724_CH6_TIME_OVER_UNDER_THR_INDEX,                
        CVT_V1724_CH6_STATUS_INDEX,                                             
        CVT_V1724_CH6_FW_REV_INDEX,                                             
        CVT_V1724_CH6_BUFF_OCCUPANCY_INDEX,                             
        CVT_V1724_CH6_DAC_CONF_INDEX,                                   
        CVT_V1724_CH6_ADC_CONF_INDEX,                                   
        CVT_V1724_CH6_RESERVED_ADC_DEBUG_INDEX,                 
        CVT_V1724_CH6_RESERVED_MEM_DATA_INDEX,                  
        CVT_V1724_CH6_RESERVED_MEM_ADDRESS_INDEX,               
//
// CH 7
        CVT_V1724_CH7_RESERVED_RND_ACC_INDEX,                   
        CVT_V1724_CH7_THRESHOLD_INDEX,                                  
        CVT_V1724_CH7_TIME_OVER_UNDER_THR_INDEX,                
        CVT_V1724_CH7_STATUS_INDEX,                                             
        CVT_V1724_CH7_FW_REV_INDEX,                                             
        CVT_V1724_CH7_BUFF_OCCUPANCY_INDEX,                             
        CVT_V1724_CH7_DAC_CONF_INDEX,                                   
        CVT_V1724_CH7_ADC_CONF_INDEX,                                   
        CVT_V1724_CH7_RESERVED_ADC_DEBUG_INDEX,                 
        CVT_V1724_CH7_RESERVED_MEM_DATA_INDEX,                  
        CVT_V1724_CH7_RESERVED_MEM_ADDRESS_INDEX,               
//
//
        CVT_V1724_LAST_INDEX,                                                   
} CVT_V1724_REG_INDEX;
                                                                                                
#define CVT_V1724_MAX_CHANNEL                   8                       



typedef enum
{
        CVT_V1724_VME_CTRL_INT_LEVEL_MSK                = 0x0007,               
        CVT_V1724_VME_CTRL_BERR_ENABLE_MSK              = 0x0010,               
        CVT_V1724_VME_CTRL_ALIGN64_MSK                  = 0x0020,               
        CVT_V1724_VME_CTRL_RELOC_MSK                    = 0x0040,               
} CVT_V1724_VME_CONTROL_MSK;

#define CVT_V1724_GET_INT_LEVEL( reg)                   (((UINT32)reg)& CVT_V1724_VME_CTRL_INT_LEVEL_MSK)                                                                                                                                               
#define CVT_V1724_SET_INT_LEVEL( reg, value)    reg= (((UINT32)reg)& ~CVT_V1724_VME_CTRL_INT_LEVEL_MSK)| ((UINT32)value& CVT_V1724_VME_CTRL_INT_LEVEL_MSK)                              



typedef enum
{
        CVT_V1724_VME_STS_DATA_READY_MSK                = 0x0001,               
        CVT_V1724_VME_STS_FULL_MSK                              = 0x0002,               
        CVT_V1724_VME_STS_BERR_FLAG_MSK                 = 0x0004,               
        CVT_V1724_VME_STS_PURGED_MSK                    = 0x0008,               
} CVT_V1724_VME_STATUS_MSK;



typedef enum
{
        CVT_V1724_TRGEN_CH0_MSK                         = 0x00000001,           
        CVT_V1724_TRGEN_CH1_MSK                         = 0x00000002,           
        CVT_V1724_TRGEN_CH2_MSK                         = 0x00000004,           
        CVT_V1724_TRGEN_CH3_MSK                         = 0x00000008,           
        CVT_V1724_TRGEN_CH4_MSK                         = 0x00000010,           
        CVT_V1724_TRGEN_CH5_MSK                         = 0x00000020,           
        CVT_V1724_TRGEN_CH6_MSK                         = 0x00000040,           
        CVT_V1724_TRGEN_CH7_MSK                         = 0x00000080,           
        CVT_V1724_TRGEN_EXT_MSK                         = 0x40000000,           
        CVT_V1724_TRGEN_SW_MSK                          = 0x80000000,           
} CVT_V1724_TRIGGER_SRC_ENABLE_MSK;



typedef enum
{
        CVT_V1724_FPTRGEN_CH0_MSK                       = 0x00000001,           
        CVT_V1724_FPTRGEN_CH1_MSK                       = 0x00000002,           
        CVT_V1724_FPTRGEN_CH2_MSK                       = 0x00000004,           
        CVT_V1724_FPTRGEN_CH3_MSK                       = 0x00000008,           
        CVT_V1724_FPTRGEN_CH4_MSK                       = 0x00000010,           
        CVT_V1724_FPTRGEN_CH5_MSK                       = 0x00000020,           
        CVT_V1724_FPTRGEN_CH6_MSK                       = 0x00000040,           
        CVT_V1724_FPTRGEN_CH7_MSK                       = 0x00000080,           
        CVT_V1724_FPTRGEN_EXT_MSK                       = 0x40000000,           
        CVT_V1724_FPTRGEN_SW_MSK                        = 0x80000000,           
} CVT_V1724_FP_TRIGGER_OUT_ENABLE_MSK;



typedef enum
{
        CVT_V1724_BROAD_CHCTRL_GATE_MODE_MSK                    = 0x00000001,   
        CVT_V1724_BROAD_CHCTRL_TRG_OVERLAP_MSK                  = 0x00000002,   
        CVT_V1724_BROAD_CHCTRL_MEM_ENABLE_MSK                   = 0x00000004,   
        CVT_V1724_BROAD_CHCTRL_MEM_ACC_MODE_MSK                 = 0x00000010,   
        CVT_V1724_BROAD_CHCTRL_TRG_IN_EN_MSK                    = 0x00000020,   
        CVT_V1724_BROAD_CHCTRL_TRG_OUT_THR_MSK                  = 0x00000040,   
        CVT_V1724_BROAD_CHCTRL_TRG_OUT_EN_MSK                   = 0x00000080,   
} CVT_V1724_BROAD_CH_CONTROL_MSK;



typedef enum
{
        CVT_V1724_BROAD_CHRNDACC_BLOCK_ADD_MSK          = 0x000003FF,   
        CVT_V1724_BROAD_CHRNDACC_SAMPLE_NUM_MSK         = 0x003FFC00,   
        CVT_V1724_BROAD_CHRNDACC_OFFSET_MSK                     = 0xFFC00000,   
} CVT_V1724_BROAD_CH_RND_ACC_MSK;

#define CVT_V1724_GET_CH_RND_ACC_BLOCK_ADD( reg)                        (((UINT32)reg)& CVT_V1724_BROAD_CHRNDACC_BLOCK_ADD_MSK)                                                                                                                                                         
#define CVT_V1724_SET_CH_RND_ACC_BLOCK_ADD( reg, value)         reg= (((UINT32)reg)& ~CVT_V1724_BROAD_CHRNDACC_BLOCK_ADD_MSK)| ((UINT32)value& CVT_V1724_BROAD_CHRNDACC_BLOCK_ADD_MSK)                          
#define CVT_V1724_GET_CH_RND_ACC_SAMPLE_NUM( reg)                       ((((UINT32)reg)& CVT_V1724_BROAD_CHRNDACC_SAMPLE_NUM_MSK)>> 10)                                                                                                                                         
#define CVT_V1724_SET_CH_RND_ACC_SAMPLE_NUM( reg, value)        reg= (((UINT32)reg)& ~CVT_V1724_BROAD_CHRNDACC_SAMPLE_NUM_MSK)| ((((UINT32)value)<< 10)& CVT_V1724_BROAD_CHRNDACC_SAMPLE_NUM_MSK)       
#define CVT_V1724_GET_CH_RND_ACC_OFFSET( reg)                           ((((UINT32)reg)& CVT_V1724_BROAD_CHRNDACC_OFFSET_MSK)>> 22)                                                                                                                                                     
#define CVT_V1724_SET_CH_RND_ACC_OFFSET( reg, value)            reg= (((UINT32)reg)& ~CVT_V1724_BROAD_CHRNDACC_OFFSET_MSK)| ((((UINT32)value)<< 22)& CVT_V1724_BROAD_CHRNDACC_OFFSET_MSK)                       



typedef enum
{
        CVT_V1724_ACQCTRL_ACQ_MODE_MSK                  = 0x00000003,   
        CVT_V1724_ACQCTRL_START_MSK                             = 0x00000004,   
        CVT_V1724_ACQCTRL_EVENT_COUNTER_ALL_MSK = 0x00000008,   
        CVT_V1724_ACQCTRL_DOWNSAMPLE_MSK                = 0x00000010,   
} CVT_V1724_ACQ_CONTROL_MSK;

#define CVT_V1724_GET_ACQCTRL_ACQ_MODE( reg)                    (((UINT32)reg)& CVT_V1724_ACQCTRL_ACQ_MODE_MSK)                                                                                                                                         
#define CVT_V1724_SET_ACQCTRL_ACQ_MODE( reg, value)             reg= (((UINT32)reg)& ~CVT_V1724_ACQCTRL_ACQ_MODE_MSK)| ((UINT32)value& CVT_V1724_ACQCTRL_ACQ_MODE_MSK)                          



typedef enum
{
        CVT_V1724_ACQCTRL_ACQ_MODE_REGISTER_CTRL                = 0,    
        CVT_V1724_ACQCTRL_ACQ_MODE_S_IN_CTRL                    = 1,    
        CVT_V1724_ACQCTRL_ACQ_MODE_S_IN_GATE                    = 2,    
        CVT_V1724_ACQCTRL_ACQ_MODE_MULTIBOARD_SYNC              = 3,    
} CVT_V1724_ACQ_CONTROL_ACQ_MODES;



typedef enum
{
        CVT_V1724_ACQSTS_MEB_NOT_EMPTY_MSK              = 0x00000001,   
        CVT_V1724_ACQSTS_MEB_FULL_MSK                   = 0x00000002,   
        CVT_V1724_ACQSTS_RUN_MSK                                = 0x00000004,   
        CVT_V1724_ACQSTS_EVENT_RDY_MSK                  = 0x00000008,   
        CVT_V1724_ACQSTS_EVENT_FULL_MSK                 = 0x00000010,   
        CVT_V1724_ACQSTS_S_IN_MSK                               = 0x00008000,   
} CVT_V1724_ACQ_STATUS_MSK;



typedef enum
{
        CVT_V1724_CHEN_CH0_MSK                          = 0x0001,               
        CVT_V1724_CHEN_CH1_MSK                          = 0x0002,               
        CVT_V1724_CHEN_CH2_MSK                          = 0x0004,               
        CVT_V1724_CHEN_CH3_MSK                          = 0x0008,               
        CVT_V1724_CHEN_CH4_MSK                          = 0x0010,               
        CVT_V1724_CHEN_CH5_MSK                          = 0x0020,               
        CVT_V1724_CHEN_CH6_MSK                          = 0x0040,               
        CVT_V1724_CHEN_CH7_MSK                          = 0x0080,               
} CVT_V1724_CH_ENABLE_MSK;



typedef enum
{
        CVT_V1724_CHCONF_DITHER_MSK                     = 0x00000001,   
        CVT_V1724_CHCONF_CLK_DUTY_STAB_MSK      = 0x00000002,   
        CVT_V1724_CHCONF_RND_MSK                        = 0x00000004,   
} CVT_V1724_CH_CONF_MSK;



typedef enum
{
        CVT_V1724_FPIO_MSK                      = 0x0000FFFF,                   
} CVT_V1724_FRONT_PANEL_IO_MSK;

#define CVT_V1724_GET_FRONT_PANEL_IO( reg)                      (((UINT32)reg)& CVT_V1724_FPIO_MSK)                                                                                                     
#define CVT_V1724_SET_FRONT_PANEL_IO( reg, value)       reg= (((UINT32)reg)& ~CVT_V1724_FPIO_MSK)| ((UINT32)value& CVT_V1724_FPIO_MSK)          



typedef enum
{
        CVT_V1724_FPIO_CTRL_TTL_MSK                     = 0x00000001,   
        CVT_V1724_FPIO_CTRL_OUT_DIS_MSK         = 0x00000002,   
        CVT_V1724_FPIO_CTRL_DIR_MSK                     = 0x0000003C,   
        CVT_V1724_FPIO_CTRL_MODE_MSK            = 0x000000C0,   
} CVT_V1724_FRONT_PANEL_IO_CTRL_MSK;

#define CVT_V1724_GET_FPIO_CTRL_DIR( reg)                       ((((UINT32)reg)& CVT_V1724_FPIO_CTRL_DIR_MSK)>> 2)                                                                                                                      
#define CVT_V1724_SET_FPIO_CTRL_DIR( reg, value)        reg= (((UINT32)reg)& ~CVT_V1724_FPIO_CTRL_DIR_MSK)| ((((UINT32)value)<< 2)& CVT_V1724_FPIO_CTRL_DIR_MSK)        
#define CVT_V1724_GET_FPIO_CTRL_MODE( reg)                      ((((UINT32)reg)& CVT_V1724_FPIO_CTRL_MODE_MSK)>> 6)                                                                                                                     
#define CVT_V1724_SET_FPIO_CTRL_MODE( reg, value)       reg= (((UINT32)reg)& ~CVT_V1724_FPIO_CTRL_MODE_MSK)| ((((UINT32)value)<< 6)& CVT_V1724_FPIO_CTRL_MODE_MSK)      



typedef enum
{
        CVT_V1724_FPIO_MODES_GPIO                       = 0,                    
        CVT_V1724_FPIO_MODES_PROGIO                     = 1,                    
        CVT_V1724_FPIO_MODES_PATTERN            = 2,                    
} CVT_V1724_FRONT_PANEL_IO_MODES;



typedef enum
{
        CVT_V1724_CHDAC_DATA_MSK                        = 0x0000FFFF,   
        CVT_V1724_CHDAC_SET_A_MSK                       = 0x00100000,   
        CVT_V1724_CHDAC_SET_B_MSK                       = 0x00240000,   
} CVT_V1724_DAC_CONF_MSK;

#define CVT_V1724_GET_CH_DAC_CONF( reg)                 (((UINT32)reg)& CVT_V1724_CHDAC_DATA_MSK)                                                                                                                               
#define CVT_V1724_SET_CH_DAC_CONF( reg, value)  reg= (((UINT32)reg)& ~CVT_V1724_CHDAC_DATA_MSK)| ((UINT32)value& CVT_V1724_CHDAC_DATA_MSK)                              



typedef enum
{
        CVT_V1724_CHSTS_FIFO_FULL_MSK           = 0x00000001,   
        CVT_V1724_CHSTS_FIFO_EMPTY_MSK          = 0x00000002,   
        CVT_V1724_CHSTS_DAC_BUSY_MSK            = 0x00000004,   
        CVT_V1724_CHSTS_BIST_END_MSK            = 0x00000008,   
        CVT_V1724_CHSTS_BIST_OK_MSK                     = 0x00000010,   
        CVT_V1724_CHSTS_BLOCK_REM_OK_MSK        = 0x00000020,   
} CVT_V1724_CH_STATUS_MSK;
  


typedef enum
{
        CVT_V1724_CHBKSZ_512K= 0,                       
        CVT_V1724_CHBKSZ_256K,                          
        CVT_V1724_CHBKSZ_128K,                          
        CVT_V1724_CHBKSZ_64K,                           
        CVT_V1724_CHBKSZ_32K,                           
        CVT_V1724_CHBKSZ_16K,                           
        CVT_V1724_CHBKSZ_8K,                            
        CVT_V1724_CHBKSZ_4K,                            
        CVT_V1724_CHBKSZ_2K,                            
        CVT_V1724_CHBKSZ_1K,                            
        CVT_V1724_CHBKSZ_512,                           
} CVT_V1724_CH_BLKSIZE;



static const UINT32 CVT_V1724_CH_SAMPLE_SIZE[]=
{
        512* 1024,                                                      
        256* 1024,                                                      
        128* 1024,                                                      
         64* 1024,                                                      
         32* 1024,                                                      
         16* 1024,                                                      
          8* 1024,                                                      
          4* 1024,                                                      
          2* 1024,                                                      
             1024,                                                      
              512,                                                      
};



typedef enum
{
        CVT_V1724_MCST_CBLT_ADD_MSK                     = 0x000000FF,           
        CVT_V1724_MCST_CBLT_CTRL_MSK            = 0x00000300,           
} CVT_V1724_MCST_CBLT_ADD_CTRL_MSK;

#define CVT_V1724_GET_MCST_CBLT_ADD( reg)                       (((UINT32)reg)& CVT_V1724_MCST_CBLT_ADD_MSK)                                                                                                                                            
#define CVT_V1724_SET_MCST_CBLT_ADD( reg, value)                reg= (((UINT32)reg)& ~CVT_V1724_MCST_CBLT_ADD_MSK)| ((UINT32)value& CVT_V1724_MCST_CBLT_ADD_MSK)                                
#define CVT_V1724_GET_MCST_CBLT_CTRL( reg)                      ((((UINT32)reg)& CVT_V1724_MCST_CBLT_CTRL_MSK)>> 8)                                                                                                                                     
#define CVT_V1724_SET_MCST_CBLT_CTRL( reg, value)       reg= (((UINT32)reg)& ~CVT_V1724_MCST_CBLT_CTRL_MSK)| ((((UINT32)value)<< 8)& CVT_V1724_MCST_CBLT_CTRL_MSK)                      



typedef enum
{
        CVT_V1724_MCST_CBLT_CTRL_DISABLED_BOARD                 = 0,            
        CVT_V1724_MCST_CBLT_CTRL_LAST_BOARD                             = 1,            
        CVT_V1724_MCST_CBLT_CTRL_FIRST_BOARD                    = 2,            
        CVT_V1724_MCST_CBLT_CTRL_MID_BOARD                              = 3,            
} CVT_V1724_MCST_CBLT_CTRL_BOARDS;



#define V1724_FLASH_PAGE_SIZE                                   264                             



typedef enum
{
        CVT_V1724_FOP_PAGE_ERASE                                        = 0x0081,               
        CVT_V1724_FOP_PAGE_PROG_TH_BUF1                         = 0x0082,               
        CVT_V1724_FOP_PAGE_READ                                         = 0x00D2,               
} CVT_V1724_FLASH_OPCODES;



typedef enum
{
        CVT_V1724_FB_STANDARD                                           = 48,                   
        CVT_V1724_FB_BACKUP                                                     = 1048,                 
} CVT_V1724_FLASH_BANK;



typedef enum
{
        CVT_V1724_FLEN_EN_MSK                           = 0x00000001,   
} CVT_V1724_FLASH_EN_MSK;



typedef struct
{
        UINT8 m_chksum;                                                 
        UINT32 m_chksum_len;                                    
        UINT32 m_const;                                                 
        UINT8 m_c_code;                                                 
        UINT8 m_r_code;                                                 
        UINT32 m_OUI;                                                   
        UINT8 m_version;                                                
        UINT32 m_board_id;                                              
        UINT32 m_revision;                                              
        UINT16 m_serial;                                                
} CVT_V1724_ROM_CONFIG;

// Output buffer macros

#define V1724_HEADER_TAG_MSK                            0xA0000000              
#define IS_HEADER_TAG(data_0)                           ((data_0& 0xF0000000)== V1724_HEADER_TAG_MSK)                           
#define GET_EVENT_TAG(data_0)                           ((UINT32)((((UINT32)data_0)>>28)& 0x0000000f))                          
#define GET_EVENT_BOARD_ID(data_0)                      ((UINT32)((((UINT32)data_0)>>23)& 0x0000001f))                          
#define GET_EVENT_SIZE(data_0)                          ((UINT32)(((UINT32)data_0)& 0x007fffff))                                        
#define GET_EVENT_ACTIVE_CHANNELS(data_1)       ((UINT32)(((UINT32)data_1)& 0x000000ff))                                        
#define GET_EVENT_COUNT(data_2)                         ((UINT32)(((UINT32)data_2)& 0x00ffffff))                                        
#define GET_EVENT_TRIGGER_TIME_TAG(data_3)      ((UINT32)(((UINT32)data_3)& 0xffffffff))                                        
#if defined (__GNUC__)
        #define         PACKED_1                __attribute__ ((packed, aligned(1)))
        #define         _INLINE_                __inline__ 
#else
        #define         PACKED_1
        #define         _INLINE_                
#endif
#if defined(WIN32)|| defined(_WIN32_WCE)
        #pragma pack(push)
        #pragma pack(1)
#endif


#define CVT_V1724_MAX_BLT_EVENT_NUM             4               



typedef union PACKED_1
{
        struct                                                                          
        {
                union
                {
                        struct
                        {
                                UINT32 m_event_size: 23 ;               /* Event size */                
                                UINT32 m_board_id: 5 ;                  /* Board Id */          
                                UINT32 m_header_tag: 4;                 /* Header tag */                
                        } m_fields ;
                        UINT32 m_DWORD;
                } m_HEADER_0;
                union
                {
                        struct
                        {
                                UINT32 m_active_channel_msk: 8 ;        /* Active channels msk */               
                                UINT32 m_reserved: 24;                          /* reserved */          
                        } m_fields ;
                        UINT32 m_DWORD;
                } m_HEADER_1;
                union
                {
                        struct
                        {
                                UINT32 m_event_counter: 24 ;            /* Event counter */             
                                DWORD   : 8;                                            /* undefined */         
                        } m_fields ;
                        UINT32 m_DWORD;
                } m_HEADER_2;
                union
                {
                        struct
                        {
                                UINT32 m_trigger_time_tag: 32;          /* Timestamp */         
                        } m_fields ;
                        UINT32 m_DWORD;
                } m_HEADER_3;
        } m_fields;
        UINT32 m_DWORD[ 4];
} CVT_V1724_HEADER;

#if defined(WIN32)|| defined(_WIN32_WCE)
        #pragma pack(pop)
#endif


// Global variables declaration

// Global methods declaration

//
//     B O A R D S   H A N D L I N G
//



BOOL cvt_V1724_open( cvt_V1724_data* p_data, UINT16 base_address, long vme_handle);



BOOL cvt_V1724_close( cvt_V1724_data* p_data);

//
//     L E V E L   0   A P I s
//


//
//     L E V E L   1   A P I s
//

        
//
//     L E V E L   2   A P I s
//




BOOL cvt_V1724_read_data( cvt_V1724_data* p_data, UINT32* p_ch_max_samples, UINT32* p_num_events);



BOOL cvt_V1724_get_buffer_cache( cvt_V1724_data* p_data, UINT16 event_index, UINT8 ch_index, UINT16* p_buff, UINT32* p_buff_size, UINT8 *p_board_id, UINT32* p_trigger_time_tag, UINT32* p_event_counter);



BOOL cvt_V1724_set_trigger_mode( cvt_V1724_data* p_data, BOOL falling_edge_enable, BOOL trigger_in_enable, BOOL trigger_out_enable, BOOL ext_trigger_enable, BOOL sw_trigger_enable, UINT8 ch_trigger_enable_msk, BOOL trigger_overlap_enable, UINT32 post_trigger);



BOOL cvt_V1724_get_trigger_mode( cvt_V1724_data* p_data, BOOL *p_falling_edge_enable, BOOL *p_trigger_in_enable, BOOL *p_trigger_out_enable, BOOL *p_ext_trigger_enable, BOOL *p_sw_trigger_enable, UINT8 *p_ch_trigger_enable_msk, BOOL *p_trigger_overlap_enable, UINT32 *p_post_trigger);



BOOL cvt_V1724_set_trigger_mode( cvt_V1724_data* p_data, BOOL falling_edge_enable, BOOL trigger_in_enable, BOOL trigger_out_enable, BOOL ext_trigger_enable, BOOL sw_trigger_enable, UINT8 ch_trigger_enable_msk, BOOL trigger_overlap_enable, UINT32 post_trigger);



BOOL cvt_V1724_get_fp_trigger_out( cvt_V1724_data* p_data, BOOL *p_ext_trigger_enable, BOOL *p_sw_trigger_enable, UINT8 *p_ch_trigger_enable_msk);



BOOL cvt_V1724_set_fp_trigger_out( cvt_V1724_data* p_data, BOOL ext_trigger_enable, BOOL sw_trigger_enable, UINT8 ch_trigger_enable_msk);



BOOL cvt_V1724_start_acquisition( cvt_V1724_data* p_data, UINT8 ch_msk);



BOOL cvt_V1724_stop_acquisition( cvt_V1724_data* p_data);



BOOL cvt_V1724_set_acquisition_mode( cvt_V1724_data* p_data, BOOL sample_enable, CVT_V1724_CH_BLKSIZE block_size, CVT_V1724_ACQ_CONTROL_ACQ_MODES acquisition_mode, BOOL count_all_trigger, UINT32 downsample_factor);



BOOL cvt_V1724_get_acquisition_mode( cvt_V1724_data* p_data, BOOL *p_sample_enable, CVT_V1724_CH_BLKSIZE *p_block_size);



BOOL cvt_V1724_get_acquisition_status( cvt_V1724_data* p_data, BOOL *p_is_MEB_not_empty, BOOL *p_is_MEB_full, BOOL *p_is_running, BOOL *p_some_event_ready, BOOL *p_event_full, BOOL *p_s_in);



BOOL cvt_V1724_set_dither_enable( cvt_V1724_data* p_data, UINT8 ch_msk, BOOL dither_value);



BOOL cvt_V1724_get_dither_enable( cvt_V1724_data* p_data, UINT8 ch_index, BOOL *p_dither_value);



BOOL cvt_V1724_set_adc_conf( cvt_V1724_data* p_data, UINT8 ch_msk, BOOL dither_value, BOOL clk_duty_stab_value, BOOL randomize_value);



BOOL cvt_V1724_get_adc_conf( cvt_V1724_data* p_data, UINT8 ch_index, BOOL *p_dither_value, BOOL *p_clk_duty_stab_value, BOOL *p_randomize_value);



BOOL cvt_V1724_set_interrupt( cvt_V1724_data* p_data, UINT8 level, UINT32 status_id, UINT16 event_number);



BOOL cvt_V1724_get_interrupt( cvt_V1724_data* p_data, UINT8 *p_level, UINT32 *p_status_id, UINT16 *p_event_number);



BOOL cvt_V1724_set_readout_mode( cvt_V1724_data* p_data, BOOL enable_bus_error, UINT32 BLT_event_number);



BOOL cvt_V1724_get_readout_mode( cvt_V1724_data* p_data, BOOL *p_enable_bus_error, UINT32 *p_BLT_event_number);



BOOL cvt_V1724_software_reset( cvt_V1724_data* p_data);



BOOL cvt_V1724_data_clear( cvt_V1724_data* p_data);



BOOL cvt_V1724_set_channel_offset( cvt_V1724_data* p_data, UINT8 ch_msk, UINT16 offset_value);



BOOL cvt_V1724_get_channel_offset( cvt_V1724_data* p_data, UINT8 ch_index, UINT16 *p_offset_value);



BOOL cvt_V1724_set_channel_trigger( cvt_V1724_data* p_data, UINT8 ch_msk, UINT32 trigger_threshold, UINT32 threshold_samples);



BOOL cvt_V1724_get_channel_trigger( cvt_V1724_data* p_data, UINT8 ch_index, UINT32 *p_trigger_threshold, UINT32 *p_threshold_samples);



BOOL cvt_V1724_set_front_panel_IO( cvt_V1724_data* p_data, BOOL use_TTL, BOOL out_en, UINT8 dir_msk, CVT_V1724_FRONT_PANEL_IO_MODES mode);



BOOL cvt_V1724_get_front_panel_IO( cvt_V1724_data* p_data, BOOL *p_use_TTL, BOOL *p_is_out_en, UINT8 *p_dir_msk, CVT_V1724_FRONT_PANEL_IO_MODES *p_mode);


BOOL cvt_V1724_software_trigger( cvt_V1724_data* p_data);



BOOL cvt_V1724_get_channel_status( cvt_V1724_data* p_data, UINT8 ch_index, BOOL *p_is_dac_busy, BOOL *p_is_fifo_full, BOOL *p_is_fifo_almost_full, BOOL *p_is_block_remove_ok);



BOOL cvt_V1724_get_system_info( cvt_V1724_data* p_data, UINT16 *p_firmware_rev, CVT_V1724_ROM_CONFIG *p_rom_config);



BOOL cvt_V1724_get_channel_info( cvt_V1724_data* p_data, UINT8 ch_index, UINT16 *p_firmware_rev);



BOOL cvt_V1724_set_MCST_CBLT( cvt_V1724_data* p_data, UINT8 address, MCST_CBLT_board_pos pos);



BOOL cvt_V1724_get_MCST_CBLT( cvt_V1724_data* p_data, UINT8 *p_address, MCST_CBLT_board_pos *p_pos);



BOOL cvt_V1724_write_flash_page( cvt_V1724_data* p_data, const UINT8* page_buff, UINT32 page_index);



BOOL cvt_V1724_read_flash_page( cvt_V1724_data* p_data, UINT8* page_buff, UINT32 page_index);



BOOL cvt_V1724_erase_flash_page( cvt_V1724_data* p_data, UINT32 page_index);



BOOL cvt_V1724_fw_upgrade( cvt_V1724_data* p_data, const UINT8* data_buff, UINT32 data_size, CVT_V1724_FLASH_BANK flash_bank, BOOL (* call_back)(UINT32 written_bytes) );

#endif  // __CVT_V1724_DEF_H

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