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00015 #include <memory.h>
00016 #include <string.h>
00017 #include "cvt_V1724.h"
00018
00020
00022
00023
00025
00027
00029
00034
00035 static const cvt_reg_table CVT_V1724_REG_TABLE[ CVT_V1724_LAST_INDEX]=
00036 {
00037
00038
00039 {CVT_V1724_OUT_BUFFER_ADD, CVT_V1724_OUT_BUFFER_AM, CVT_V1724_OUT_BUFFER_DATA_SIZE},
00041
00042
00043 {CVT_V1724_BROAD_CH_CTRL_ADD, CVT_V1724_BROAD_CH_CTRL_AM, CVT_V1724_BROAD_CH_CTRL_DATA_SIZE},
00044 {CVT_V1724_BROAD_CH_SET_CTRL_ADD, CVT_V1724_BROAD_CH_SET_CTRL_AM, CVT_V1724_BROAD_CH_SET_CTRL_DATA_SIZE},
00045 {CVT_V1724_BROAD_CH_CLEAR_CTRL_ADD, CVT_V1724_BROAD_CH_CLEAR_CTRL_AM, CVT_V1724_BROAD_CH_CLEAR_CTRL_DATA_SIZE},
00046 {CVT_V1724_BROAD_CH_BUFF_SIZE_ADD, CVT_V1724_BROAD_CH_BUFF_SIZE_AM, CVT_V1724_BROAD_CH_BUFF_SIZE_DATA_SIZE},
00047 {CVT_V1724_BROAD_CH_BUFF_FLUSH_ADD, CVT_V1724_BROAD_CH_BUFF_FLUSH_AM, CVT_V1724_BROAD_CH_BUFF_FLUSH_DATA_SIZE},
00048 {CVT_V1724_BROAD_CH_RND_ACC_ADD, CVT_V1724_BROAD_CH_RND_ACC_AM, CVT_V1724_BROAD_CH_RND_ACC_DATA_SIZE},
00049
00050
00051 {CVT_V1724_ACQ_CONTROL_ADD, CVT_V1724_ACQ_CONTROL_AM, CVT_V1724_ACQ_CONTROL_DATA_SIZE},
00052 {CVT_V1724_ACQ_STATUS_ADD, CVT_V1724_ACQ_STATUS_AM, CVT_V1724_ACQ_STATUS_DATA_SIZE},
00053 {CVT_V1724_SW_TRIGGER_ADD, CVT_V1724_SW_TRIGGER_AM, CVT_V1724_SW_TRIGGER_DATA_SIZE},
00054 {CVT_V1724_TRIGGER_SRC_ENABLE_ADD, CVT_V1724_TRIGGER_SRC_ENABLE_AM, CVT_V1724_TRIGGER_SRC_ENABLE_DATA_SIZE},
00055 {CVT_V1724_FP_TRIGGER_OUT_ENABLE_ADD, CVT_V1724_FP_TRIGGER_OUT_ENABLE_AM, CVT_V1724_FP_TRIGGER_OUT_ENABLE_DATA_SIZE},
00056 {CVT_V1724_POST_TRIG_ADD, CVT_V1724_POST_TRIG_AM, CVT_V1724_POST_TRIG_DATA_SIZE},
00057 {CVT_V1724_FRONT_PANEL_IO_ADD, CVT_V1724_FRONT_PANEL_IO_AM, CVT_V1724_FRONT_PANEL_IO_DATA_SIZE},
00058 {CVT_V1724_FRONT_PANEL_IO_CTRL_ADD, CVT_V1724_FRONT_PANEL_IO_CTRL_AM, CVT_V1724_FRONT_PANEL_IO_CTRL_DATA_SIZE},
00059 {CVT_V1724_CH_ENABLE_ADD, CVT_V1724_CH_ENABLE_AM, CVT_V1724_CH_ENABLE_DATA_SIZE},
00060 {CVT_V1724_FW_REV_ADD, CVT_V1724_FW_REV_AM, CVT_V1724_FW_REV_DATA_SIZE},
00061 {CVT_V1724_DOWNSAMPLE_FACT_ADD, CVT_V1724_DOWNSAMPLE_FACT_AM, CVT_V1724_DOWNSAMPLE_FACT_DATA_SIZE},
00062 {CVT_V1724_EVENT_STORED_ADD, CVT_V1724_EVENT_STORED_AM, CVT_V1724_EVENT_STORED_DATA_SIZE},
00064 {CVT_V1724_VME_CONTROL_ADD, CVT_V1724_VME_CONTROL_AM, CVT_V1724_VME_CONTROL_DATA_SIZE},
00065 {CVT_V1724_VME_STATUS_ADD, CVT_V1724_VME_STATUS_AM, CVT_V1724_VME_STATUS_DATA_SIZE},
00066 {CVT_V1724_BOARD_ID_ADD, CVT_V1724_BOARD_ID_AM, CVT_V1724_BOARD_ID_DATA_SIZE},
00067 {CVT_V1724_MCST_CBLT_ADD_CTRL_ADD, CVT_V1724_MCST_CBLT_ADD_CTRL_AM, CVT_V1724_MCST_CBLT_ADD_CTRL_DATA_SIZE},
00068 {CVT_V1724_RELOCATION_ADDRESS_ADD, CVT_V1724_RELOCATION_ADDRESS_AM, CVT_V1724_RELOCATION_ADDRESS_DATA_SIZE},
00069 {CVT_V1724_INT_STATUS_ID_ADD, CVT_V1724_INT_STATUS_ID_AM, CVT_V1724_INT_STATUS_ID_DATA_SIZE},
00070 {CVT_V1724_INT_EVENT_NUM_ADD, CVT_V1724_INT_EVENT_NUM_AM, CVT_V1724_INT_EVENT_NUM_DATA_SIZE},
00071 {CVT_V1724_BLT_EVENT_NUM_ADD, CVT_V1724_BLT_EVENT_NUM_AM, CVT_V1724_BLT_EVENT_NUM_DATA_SIZE},
00072 {CVT_V1724_SCRATCH_ADD, CVT_V1724_SCRATCH_AM, CVT_V1724_SCRATCH_DATA_SIZE},
00073 {CVT_V1724_SW_RESET_ADD, CVT_V1724_SW_RESET_AM, CVT_V1724_SW_RESET_DATA_SIZE},
00074 {CVT_V1724_SW_CLEAR_ADD, CVT_V1724_SW_CLEAR_AM, CVT_V1724_SW_CLEAR_DATA_SIZE},
00075 {CVT_V1724_FLASH_EN_ADD, CVT_V1724_FLASH_EN_AM, CVT_V1724_FLASH_EN_DATA_SIZE},
00076 {CVT_V1724_FLASH_DATA_ADD, CVT_V1724_FLASH_DATA_AM, CVT_V1724_FLASH_DATA_DATA_SIZE},
00077 {CVT_V1724_RELOAD_CONFIG_ADD, CVT_V1724_RELOAD_CONFIG_AM, CVT_V1724_RELOAD_CONFIG_DATA_SIZE},
00078 {CVT_V1724_BASE_ADDRESS_ADD, CVT_V1724_BASE_ADDRESS_AM, CVT_V1724_BASE_ADDRESS_DATA_SIZE},
00079 {CVT_V1724_ROM_CHKSUM_ADD, CVT_V1724_ROM_CHKSUM_AM, CVT_V1724_ROM_CHKSUM_DATA_SIZE},
00080 {CVT_V1724_ROM_CHKSUM_LEN_2_ADD, CVT_V1724_ROM_CHKSUM_LEN_2_AM, CVT_V1724_ROM_CHKSUM_LEN_2_DATA_SIZE},
00081 {CVT_V1724_ROM_CHKSUM_LEN_1_ADD, CVT_V1724_ROM_CHKSUM_LEN_1_AM, CVT_V1724_ROM_CHKSUM_LEN_1_DATA_SIZE},
00082 {CVT_V1724_ROM_CHKSUM_LEN_0_ADD, CVT_V1724_ROM_CHKSUM_LEN_0_AM, CVT_V1724_ROM_CHKSUM_LEN_0_DATA_SIZE},
00083 {CVT_V1724_ROM_CONST_2_ADD, CVT_V1724_ROM_CONST_2_AM, CVT_V1724_ROM_CONST_2_DATA_SIZE},
00084 {CVT_V1724_ROM_CONST_1_ADD, CVT_V1724_ROM_CONST_1_AM, CVT_V1724_ROM_CONST_1_DATA_SIZE},
00085 {CVT_V1724_ROM_CONST_0_ADD, CVT_V1724_ROM_CONST_0_AM, CVT_V1724_ROM_CONST_0_DATA_SIZE},
00086 {CVT_V1724_ROM_C_CODE_ADD, CVT_V1724_ROM_C_CODE_AM, CVT_V1724_ROM_C_CODE_DATA_SIZE},
00087 {CVT_V1724_ROM_R_CODE_ADD, CVT_V1724_ROM_R_CODE_AM, CVT_V1724_ROM_R_CODE_DATA_SIZE},
00088 {CVT_V1724_ROM_OUI_2_ADD, CVT_V1724_ROM_OUI_2_AM, CVT_V1724_ROM_OUI_2_DATA_SIZE},
00089 {CVT_V1724_ROM_OUI_1_ADD, CVT_V1724_ROM_OUI_1_AM, CVT_V1724_ROM_OUI_1_DATA_SIZE},
00090 {CVT_V1724_ROM_OUI_0_ADD, CVT_V1724_ROM_OUI_0_AM, CVT_V1724_ROM_OUI_0_DATA_SIZE},
00091 {CVT_V1724_ROM_VERSION_ADD, CVT_V1724_ROM_VERSION_AM, CVT_V1724_ROM_VERSION_DATA_SIZE},
00092 {CVT_V1724_ROM_BOARD_ID_2_ADD, CVT_V1724_ROM_BOARD_ID_2_AM, CVT_V1724_ROM_BOARD_ID_2_DATA_SIZE},
00093 {CVT_V1724_ROM_BOARD_ID_1_ADD, CVT_V1724_ROM_BOARD_ID_1_AM, CVT_V1724_ROM_BOARD_ID_1_DATA_SIZE},
00094 {CVT_V1724_ROM_BOARD_ID_0_ADD, CVT_V1724_ROM_BOARD_ID_0_AM, CVT_V1724_ROM_BOARD_ID_0_DATA_SIZE},
00095 {CVT_V1724_ROM_REVISION_3_ADD, CVT_V1724_ROM_REVISION_3_AM, CVT_V1724_ROM_REVISION_3_DATA_SIZE},
00096 {CVT_V1724_ROM_REVISION_2_ADD, CVT_V1724_ROM_REVISION_2_AM, CVT_V1724_ROM_REVISION_2_DATA_SIZE},
00097 {CVT_V1724_ROM_REVISION_1_ADD, CVT_V1724_ROM_REVISION_1_AM, CVT_V1724_ROM_REVISION_1_DATA_SIZE},
00098 {CVT_V1724_ROM_REVISION_0_ADD, CVT_V1724_ROM_REVISION_0_AM, CVT_V1724_ROM_REVISION_0_DATA_SIZE},
00099 {CVT_V1724_ROM_SERIAL_1_ADD, CVT_V1724_ROM_SERIAL_1_AM, CVT_V1724_ROM_SERIAL_1_DATA_SIZE},
00100 {CVT_V1724_ROM_SERIAL_0_ADD, CVT_V1724_ROM_SERIAL_0_AM, CVT_V1724_ROM_SERIAL_0_DATA_SIZE},
00102
00103
00104 {CVT_V1724_CH0_RESERVED_RND_ACC_ADD, CVT_V1724_CH0_RESERVED_RND_ACC_AM, CVT_V1724_CH0_RESERVED_RND_ACC_DATA_SIZE},
00105 {CVT_V1724_CH0_THRESHOLD_ADD, CVT_V1724_CH0_THRESHOLD_AM, CVT_V1724_CH0_THRESHOLD_DATA_SIZE},
00106 {CVT_V1724_CH0_TIME_OVER_UNDER_THR_ADD, CVT_V1724_CH0_TIME_OVER_UNDER_THR_AM, CVT_V1724_CH0_TIME_OVER_UNDER_THR_DATA_SIZE},
00107 {CVT_V1724_CH0_STATUS_ADD, CVT_V1724_CH0_STATUS_AM, CVT_V1724_CH0_STATUS_DATA_SIZE},
00108 {CVT_V1724_CH0_FW_REV_ADD, CVT_V1724_CH0_FW_REV_AM, CVT_V1724_CH0_FW_REV_DATA_SIZE},
00109 {CVT_V1724_CH0_BUFF_OCCUPANCY_ADD, CVT_V1724_CH0_BUFF_OCCUPANCY_AM, CVT_V1724_CH0_BUFF_OCCUPANCY_DATA_SIZE},
00110 {CVT_V1724_CH0_DAC_CONF_ADD, CVT_V1724_CH0_DAC_CONF_AM, CVT_V1724_CH0_DAC_CONF_DATA_SIZE},
00111 {CVT_V1724_CH0_ADC_CONF_ADD, CVT_V1724_CH0_ADC_CONF_AM, CVT_V1724_CH0_ADC_CONF_DATA_SIZE},
00112 {CVT_V1724_CH0_RESERVED_ADC_DEBUG_ADD, CVT_V1724_CH0_RESERVED_ADC_DEBUG_AM, CVT_V1724_CH0_RESERVED_ADC_DEBUG_DATA_SIZE},
00113 {CVT_V1724_CH0_RESERVED_MEM_DATA_ADD, CVT_V1724_CH0_RESERVED_MEM_DATA_AM, CVT_V1724_CH0_RESERVED_MEM_DATA_DATA_SIZE},
00114 {CVT_V1724_CH0_RESERVED_MEM_ADDRESS_ADD,CVT_V1724_CH0_RESERVED_MEM_ADDRESS_AM, CVT_V1724_CH0_RESERVED_MEM_ADDRESS_DATA_SIZE},
00116
00117
00118 {CVT_V1724_CH1_RESERVED_RND_ACC_ADD, CVT_V1724_CH1_RESERVED_RND_ACC_AM, CVT_V1724_CH1_RESERVED_RND_ACC_DATA_SIZE},
00119 {CVT_V1724_CH1_THRESHOLD_ADD, CVT_V1724_CH1_THRESHOLD_AM, CVT_V1724_CH1_THRESHOLD_DATA_SIZE},
00120 {CVT_V1724_CH1_TIME_OVER_UNDER_THR_ADD, CVT_V1724_CH1_TIME_OVER_UNDER_THR_AM, CVT_V1724_CH1_TIME_OVER_UNDER_THR_DATA_SIZE},
00121 {CVT_V1724_CH1_STATUS_ADD, CVT_V1724_CH1_STATUS_AM, CVT_V1724_CH1_STATUS_DATA_SIZE},
00122 {CVT_V1724_CH1_FW_REV_ADD, CVT_V1724_CH1_FW_REV_AM, CVT_V1724_CH1_FW_REV_DATA_SIZE},
00123 {CVT_V1724_CH1_BUFF_OCCUPANCY_ADD, CVT_V1724_CH1_BUFF_OCCUPANCY_AM, CVT_V1724_CH1_BUFF_OCCUPANCY_DATA_SIZE},
00124 {CVT_V1724_CH1_DAC_CONF_ADD, CVT_V1724_CH1_DAC_CONF_AM, CVT_V1724_CH1_DAC_CONF_DATA_SIZE},
00125 {CVT_V1724_CH1_ADC_CONF_ADD, CVT_V1724_CH1_ADC_CONF_AM, CVT_V1724_CH1_ADC_CONF_DATA_SIZE},
00126 {CVT_V1724_CH1_RESERVED_ADC_DEBUG_ADD, CVT_V1724_CH1_RESERVED_ADC_DEBUG_AM, CVT_V1724_CH1_RESERVED_ADC_DEBUG_DATA_SIZE},
00127 {CVT_V1724_CH1_RESERVED_MEM_DATA_ADD, CVT_V1724_CH1_RESERVED_MEM_DATA_AM, CVT_V1724_CH1_RESERVED_MEM_DATA_DATA_SIZE},
00128 {CVT_V1724_CH1_RESERVED_MEM_ADDRESS_ADD,CVT_V1724_CH1_RESERVED_MEM_ADDRESS_AM, CVT_V1724_CH1_RESERVED_MEM_ADDRESS_DATA_SIZE},
00130
00131
00132 {CVT_V1724_CH2_RESERVED_RND_ACC_ADD, CVT_V1724_CH2_RESERVED_RND_ACC_AM, CVT_V1724_CH2_RESERVED_RND_ACC_DATA_SIZE},
00133 {CVT_V1724_CH2_THRESHOLD_ADD, CVT_V1724_CH2_THRESHOLD_AM, CVT_V1724_CH2_THRESHOLD_DATA_SIZE},
00134 {CVT_V1724_CH2_TIME_OVER_UNDER_THR_ADD, CVT_V1724_CH2_TIME_OVER_UNDER_THR_AM, CVT_V1724_CH2_TIME_OVER_UNDER_THR_DATA_SIZE},
00135 {CVT_V1724_CH2_STATUS_ADD, CVT_V1724_CH2_STATUS_AM, CVT_V1724_CH2_STATUS_DATA_SIZE},
00136 {CVT_V1724_CH2_FW_REV_ADD, CVT_V1724_CH2_FW_REV_AM, CVT_V1724_CH2_FW_REV_DATA_SIZE},
00137 {CVT_V1724_CH2_BUFF_OCCUPANCY_ADD, CVT_V1724_CH2_BUFF_OCCUPANCY_AM, CVT_V1724_CH2_BUFF_OCCUPANCY_DATA_SIZE},
00138 {CVT_V1724_CH2_DAC_CONF_ADD, CVT_V1724_CH2_DAC_CONF_AM, CVT_V1724_CH2_DAC_CONF_DATA_SIZE},
00139 {CVT_V1724_CH2_ADC_CONF_ADD, CVT_V1724_CH2_ADC_CONF_AM, CVT_V1724_CH2_ADC_CONF_DATA_SIZE},
00140 {CVT_V1724_CH2_RESERVED_ADC_DEBUG_ADD, CVT_V1724_CH2_RESERVED_ADC_DEBUG_AM, CVT_V1724_CH2_RESERVED_ADC_DEBUG_DATA_SIZE},
00141 {CVT_V1724_CH2_RESERVED_MEM_DATA_ADD, CVT_V1724_CH2_RESERVED_MEM_DATA_AM, CVT_V1724_CH2_RESERVED_MEM_DATA_DATA_SIZE},
00142 {CVT_V1724_CH2_RESERVED_MEM_ADDRESS_ADD,CVT_V1724_CH2_RESERVED_MEM_ADDRESS_AM, CVT_V1724_CH2_RESERVED_MEM_ADDRESS_DATA_SIZE},
00144
00145
00146 {CVT_V1724_CH3_RESERVED_RND_ACC_ADD, CVT_V1724_CH3_RESERVED_RND_ACC_AM, CVT_V1724_CH3_RESERVED_RND_ACC_DATA_SIZE},
00147 {CVT_V1724_CH3_THRESHOLD_ADD, CVT_V1724_CH3_THRESHOLD_AM, CVT_V1724_CH3_THRESHOLD_DATA_SIZE},
00148 {CVT_V1724_CH3_TIME_OVER_UNDER_THR_ADD, CVT_V1724_CH3_TIME_OVER_UNDER_THR_AM, CVT_V1724_CH3_TIME_OVER_UNDER_THR_DATA_SIZE},
00149 {CVT_V1724_CH3_STATUS_ADD, CVT_V1724_CH3_STATUS_AM, CVT_V1724_CH3_STATUS_DATA_SIZE},
00150 {CVT_V1724_CH3_FW_REV_ADD, CVT_V1724_CH3_FW_REV_AM, CVT_V1724_CH3_FW_REV_DATA_SIZE},
00151 {CVT_V1724_CH3_BUFF_OCCUPANCY_ADD, CVT_V1724_CH3_BUFF_OCCUPANCY_AM, CVT_V1724_CH3_BUFF_OCCUPANCY_DATA_SIZE},
00152 {CVT_V1724_CH3_DAC_CONF_ADD, CVT_V1724_CH3_DAC_CONF_AM, CVT_V1724_CH3_DAC_CONF_DATA_SIZE},
00153 {CVT_V1724_CH3_ADC_CONF_ADD, CVT_V1724_CH3_ADC_CONF_AM, CVT_V1724_CH3_ADC_CONF_DATA_SIZE},
00154 {CVT_V1724_CH3_RESERVED_ADC_DEBUG_ADD, CVT_V1724_CH3_RESERVED_ADC_DEBUG_AM, CVT_V1724_CH3_RESERVED_ADC_DEBUG_DATA_SIZE},
00155 {CVT_V1724_CH3_RESERVED_MEM_DATA_ADD, CVT_V1724_CH3_RESERVED_MEM_DATA_AM, CVT_V1724_CH3_RESERVED_MEM_DATA_DATA_SIZE},
00156 {CVT_V1724_CH3_RESERVED_MEM_ADDRESS_ADD,CVT_V1724_CH3_RESERVED_MEM_ADDRESS_AM, CVT_V1724_CH3_RESERVED_MEM_ADDRESS_DATA_SIZE},
00158
00159
00160 {CVT_V1724_CH4_RESERVED_RND_ACC_ADD, CVT_V1724_CH4_RESERVED_RND_ACC_AM, CVT_V1724_CH4_RESERVED_RND_ACC_DATA_SIZE},
00161 {CVT_V1724_CH4_THRESHOLD_ADD, CVT_V1724_CH4_THRESHOLD_AM, CVT_V1724_CH4_THRESHOLD_DATA_SIZE},
00162 {CVT_V1724_CH4_TIME_OVER_UNDER_THR_ADD, CVT_V1724_CH4_TIME_OVER_UNDER_THR_AM, CVT_V1724_CH4_TIME_OVER_UNDER_THR_DATA_SIZE},
00163 {CVT_V1724_CH4_STATUS_ADD, CVT_V1724_CH4_STATUS_AM, CVT_V1724_CH4_STATUS_DATA_SIZE},
00164 {CVT_V1724_CH4_FW_REV_ADD, CVT_V1724_CH4_FW_REV_AM, CVT_V1724_CH4_FW_REV_DATA_SIZE},
00165 {CVT_V1724_CH4_BUFF_OCCUPANCY_ADD, CVT_V1724_CH4_BUFF_OCCUPANCY_AM, CVT_V1724_CH4_BUFF_OCCUPANCY_DATA_SIZE},
00166 {CVT_V1724_CH4_DAC_CONF_ADD, CVT_V1724_CH4_DAC_CONF_AM, CVT_V1724_CH4_DAC_CONF_DATA_SIZE},
00167 {CVT_V1724_CH4_ADC_CONF_ADD, CVT_V1724_CH4_ADC_CONF_AM, CVT_V1724_CH4_ADC_CONF_DATA_SIZE},
00168 {CVT_V1724_CH4_RESERVED_ADC_DEBUG_ADD, CVT_V1724_CH4_RESERVED_ADC_DEBUG_AM, CVT_V1724_CH4_RESERVED_ADC_DEBUG_DATA_SIZE},
00169 {CVT_V1724_CH4_RESERVED_MEM_DATA_ADD, CVT_V1724_CH4_RESERVED_MEM_DATA_AM, CVT_V1724_CH4_RESERVED_MEM_DATA_DATA_SIZE},
00170 {CVT_V1724_CH4_RESERVED_MEM_ADDRESS_ADD,CVT_V1724_CH4_RESERVED_MEM_ADDRESS_AM, CVT_V1724_CH4_RESERVED_MEM_ADDRESS_DATA_SIZE},
00172
00173
00174 {CVT_V1724_CH5_RESERVED_RND_ACC_ADD, CVT_V1724_CH5_RESERVED_RND_ACC_AM, CVT_V1724_CH5_RESERVED_RND_ACC_DATA_SIZE},
00175 {CVT_V1724_CH5_THRESHOLD_ADD, CVT_V1724_CH5_THRESHOLD_AM, CVT_V1724_CH5_THRESHOLD_DATA_SIZE},
00176 {CVT_V1724_CH5_TIME_OVER_UNDER_THR_ADD, CVT_V1724_CH5_TIME_OVER_UNDER_THR_AM, CVT_V1724_CH5_TIME_OVER_UNDER_THR_DATA_SIZE},
00177 {CVT_V1724_CH5_STATUS_ADD, CVT_V1724_CH5_STATUS_AM, CVT_V1724_CH5_STATUS_DATA_SIZE},
00178 {CVT_V1724_CH5_FW_REV_ADD, CVT_V1724_CH5_FW_REV_AM, CVT_V1724_CH5_FW_REV_DATA_SIZE},
00179 {CVT_V1724_CH5_BUFF_OCCUPANCY_ADD, CVT_V1724_CH5_BUFF_OCCUPANCY_AM, CVT_V1724_CH5_BUFF_OCCUPANCY_DATA_SIZE},
00180 {CVT_V1724_CH5_DAC_CONF_ADD, CVT_V1724_CH5_DAC_CONF_AM, CVT_V1724_CH5_DAC_CONF_DATA_SIZE},
00181 {CVT_V1724_CH5_ADC_CONF_ADD, CVT_V1724_CH5_ADC_CONF_AM, CVT_V1724_CH5_ADC_CONF_DATA_SIZE},
00182 {CVT_V1724_CH5_RESERVED_ADC_DEBUG_ADD, CVT_V1724_CH5_RESERVED_ADC_DEBUG_AM, CVT_V1724_CH5_RESERVED_ADC_DEBUG_DATA_SIZE},
00183 {CVT_V1724_CH5_RESERVED_MEM_DATA_ADD, CVT_V1724_CH5_RESERVED_MEM_DATA_AM, CVT_V1724_CH5_RESERVED_MEM_DATA_DATA_SIZE},
00184 {CVT_V1724_CH5_RESERVED_MEM_ADDRESS_ADD,CVT_V1724_CH5_RESERVED_MEM_ADDRESS_AM, CVT_V1724_CH5_RESERVED_MEM_ADDRESS_DATA_SIZE},
00186
00187
00188 {CVT_V1724_CH6_RESERVED_RND_ACC_ADD, CVT_V1724_CH6_RESERVED_RND_ACC_AM, CVT_V1724_CH6_RESERVED_RND_ACC_DATA_SIZE},
00189 {CVT_V1724_CH6_THRESHOLD_ADD, CVT_V1724_CH6_THRESHOLD_AM, CVT_V1724_CH6_THRESHOLD_DATA_SIZE},
00190 {CVT_V1724_CH6_TIME_OVER_UNDER_THR_ADD, CVT_V1724_CH6_TIME_OVER_UNDER_THR_AM, CVT_V1724_CH6_TIME_OVER_UNDER_THR_DATA_SIZE},
00191 {CVT_V1724_CH6_STATUS_ADD, CVT_V1724_CH6_STATUS_AM, CVT_V1724_CH6_STATUS_DATA_SIZE},
00192 {CVT_V1724_CH6_FW_REV_ADD, CVT_V1724_CH6_FW_REV_AM, CVT_V1724_CH6_FW_REV_DATA_SIZE},
00193 {CVT_V1724_CH6_BUFF_OCCUPANCY_ADD, CVT_V1724_CH6_BUFF_OCCUPANCY_AM, CVT_V1724_CH6_BUFF_OCCUPANCY_DATA_SIZE},
00194 {CVT_V1724_CH6_DAC_CONF_ADD, CVT_V1724_CH6_DAC_CONF_AM, CVT_V1724_CH6_DAC_CONF_DATA_SIZE},
00195 {CVT_V1724_CH6_ADC_CONF_ADD, CVT_V1724_CH6_ADC_CONF_AM, CVT_V1724_CH6_ADC_CONF_DATA_SIZE},
00196 {CVT_V1724_CH6_RESERVED_ADC_DEBUG_ADD, CVT_V1724_CH6_RESERVED_ADC_DEBUG_AM, CVT_V1724_CH6_RESERVED_ADC_DEBUG_DATA_SIZE},
00197 {CVT_V1724_CH6_RESERVED_MEM_DATA_ADD, CVT_V1724_CH6_RESERVED_MEM_DATA_AM, CVT_V1724_CH6_RESERVED_MEM_DATA_DATA_SIZE},
00198 {CVT_V1724_CH6_RESERVED_MEM_ADDRESS_ADD,CVT_V1724_CH6_RESERVED_MEM_ADDRESS_AM, CVT_V1724_CH6_RESERVED_MEM_ADDRESS_DATA_SIZE},
00200
00201
00202 {CVT_V1724_CH7_RESERVED_RND_ACC_ADD, CVT_V1724_CH7_RESERVED_RND_ACC_AM, CVT_V1724_CH7_RESERVED_RND_ACC_DATA_SIZE},
00203 {CVT_V1724_CH7_THRESHOLD_ADD, CVT_V1724_CH7_THRESHOLD_AM, CVT_V1724_CH7_THRESHOLD_DATA_SIZE},
00204 {CVT_V1724_CH7_TIME_OVER_UNDER_THR_ADD, CVT_V1724_CH7_TIME_OVER_UNDER_THR_AM, CVT_V1724_CH7_TIME_OVER_UNDER_THR_DATA_SIZE},
00205 {CVT_V1724_CH7_STATUS_ADD, CVT_V1724_CH7_STATUS_AM, CVT_V1724_CH7_STATUS_DATA_SIZE},
00206 {CVT_V1724_CH7_FW_REV_ADD, CVT_V1724_CH7_FW_REV_AM, CVT_V1724_CH7_FW_REV_DATA_SIZE},
00207 {CVT_V1724_CH7_BUFF_OCCUPANCY_ADD, CVT_V1724_CH7_BUFF_OCCUPANCY_AM, CVT_V1724_CH7_BUFF_OCCUPANCY_DATA_SIZE},
00208 {CVT_V1724_CH7_DAC_CONF_ADD, CVT_V1724_CH7_DAC_CONF_AM, CVT_V1724_CH7_DAC_CONF_DATA_SIZE},
00209 {CVT_V1724_CH7_ADC_CONF_ADD, CVT_V1724_CH7_ADC_CONF_AM, CVT_V1724_CH7_ADC_CONF_DATA_SIZE},
00210 {CVT_V1724_CH7_RESERVED_ADC_DEBUG_ADD, CVT_V1724_CH7_RESERVED_ADC_DEBUG_AM, CVT_V1724_CH7_RESERVED_ADC_DEBUG_DATA_SIZE},
00211 {CVT_V1724_CH7_RESERVED_MEM_DATA_ADD, CVT_V1724_CH7_RESERVED_MEM_DATA_AM, CVT_V1724_CH7_RESERVED_MEM_DATA_DATA_SIZE},
00212 {CVT_V1724_CH7_RESERVED_MEM_ADDRESS_ADD,CVT_V1724_CH7_RESERVED_MEM_ADDRESS_AM, CVT_V1724_CH7_RESERVED_MEM_ADDRESS_DATA_SIZE},
00214 };
00215
00217
00219
00221
00223
00225
00226
00227
00229
00231
00233 BOOL cvt_V1724_open( cvt_V1724_data* p_data, UINT16 base_address, long vme_handle)
00234 {
00235 const UINT32 ch_max_block_size= CVT_V1724_CH_SAMPLE_SIZE[0]* sizeof( UINT16);
00236 memset( p_data, 0, sizeof( cvt_V1724_data));
00237
00238
00239 if( !cvt_board_open( &p_data->m_common_data, base_address, vme_handle, CVT_V1724_REG_TABLE))
00240 return FALSE;
00241
00242 p_data->m_common_data.set_MCST_CBLT= ( BOOL (*)( void*, UINT8, MCST_CBLT_board_pos))cvt_V1724_set_MCST_CBLT;
00243
00244
00245 p_data->m_cache_sample_buffer_size= (( CVT_V1724_MAX_CHANNEL* ( ch_max_block_size+ sizeof( CVT_V1724_HEADER)+ 4))* 1 )>> 2;
00246 p_data->m_cache_sample_buffer= malloc( p_data->m_cache_sample_buffer_size* sizeof( UINT32));
00247 p_data->m_cache_sample_buffer_read_bytes= 0;
00248
00249 return TRUE;
00250 }
00251
00253
00255 BOOL cvt_V1724_close( cvt_V1724_data* p_data)
00256 {
00257 if( p_data->m_cache_sample_buffer)
00258 {
00259 free( p_data->m_cache_sample_buffer);
00260 p_data->m_cache_sample_buffer= NULL;
00261 p_data->m_cache_sample_buffer_size= 0;
00262 p_data->m_cache_sample_buffer_read_bytes= 0;
00263 }
00264 if( !cvt_board_close( &p_data->m_common_data))
00265 return FALSE;
00266 return TRUE;
00267 }
00268
00270
00271
00272
00274
00275
00277
00278
00279
00281
00283
00284
00285
00287
00289
00291 BOOL cvt_V1724_read_data( cvt_V1724_data* p_data, UINT32* p_ch_max_samples, UINT32* p_num_events)
00292 {
00293 const UINT32 ch_max_block_size= CVT_V1724_CH_SAMPLE_SIZE[0]* sizeof( UINT16);
00294 UINT32 BLT_event_number= 0;
00295 UINT32 new_size;
00296 CVT_V1724_HEADER* p_header;
00297 BOOL is_berr= FALSE;
00298
00299 *p_ch_max_samples= 0;
00300 *p_num_events= 0;
00301
00302
00303
00304 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_EVENT_STORED_INDEX, &BLT_event_number))
00305 {
00306 TRACE( "CVT_V1724_EVENT_STORED read failed !\n");
00307 return FALSE;
00308 }
00309 if( BLT_event_number> CVT_V1724_MAX_BLT_EVENT_NUM)
00310 BLT_event_number= CVT_V1724_MAX_BLT_EVENT_NUM;
00311 new_size= (( CVT_V1724_MAX_CHANNEL* ( ch_max_block_size+ sizeof( CVT_V1724_HEADER)+ 4))* BLT_event_number)>> 2;
00312
00313 if( p_data->m_cache_sample_buffer_size< new_size)
00314 {
00315
00316 p_data->m_cache_sample_buffer_size= new_size;
00317 p_data->m_cache_sample_buffer= realloc( p_data->m_cache_sample_buffer, p_data->m_cache_sample_buffer_size* sizeof( UINT32));
00318
00319
00320 }
00321
00322 p_data->m_cache_sample_buffer_read_bytes= 0;
00323
00324
00325 if( !cvt_FIFO_BLT_read( &p_data->m_common_data, CVT_V1724_OUT_BUFFER_ADD, p_data->m_cache_sample_buffer, p_data->m_cache_sample_buffer_size, &p_data->m_cache_sample_buffer_read_bytes, CVT_V1724_OUT_BUFFER_AM, CVT_V1724_OUT_BUFFER_DATA_SIZE, &is_berr))
00326 {
00327 p_data->m_cache_sample_buffer_read_bytes= 0;
00328 return FALSE;
00329 }
00330 if( p_data->m_cache_sample_buffer_read_bytes< sizeof( CVT_V1724_HEADER))
00331 {
00332 p_data->m_cache_sample_buffer_read_bytes= 0;
00333 return FALSE;
00334 }
00335
00336
00337 {
00338 UINT32 offset= 0;
00339 UINT8 ch_msk;
00340 int num_channels;
00341 UINT32 samples;
00342
00343 while( offset< p_data->m_cache_sample_buffer_read_bytes)
00344 {
00345 p_header= (CVT_V1724_HEADER*)(( UINT8*)p_data->m_cache_sample_buffer+ offset);
00346 if( !IS_HEADER_TAG( p_header->m_fields.m_HEADER_0.m_DWORD))
00347 {
00348
00349 p_data->m_cache_sample_buffer_read_bytes= 0;
00350 *p_ch_max_samples= 0;
00351 *p_num_events= 0;
00352 return FALSE;
00353 }
00354 ++(*p_num_events);
00355
00356 for( ch_msk= p_header->m_fields.m_HEADER_1.m_fields.m_active_channel_msk, num_channels= 0; ch_msk; ch_msk>>= 1)
00357 {
00358 if( ch_msk& 0x01)
00359 ++num_channels;
00360 }
00361 if( !num_channels)
00362 {
00363 return TRUE;
00364 }
00365 samples= ((( p_header->m_fields.m_HEADER_0.m_fields.m_event_size<< 2)- sizeof( CVT_V1724_HEADER))/ num_channels)<< 1;
00366 if( *p_ch_max_samples< samples)
00367 {
00368 *p_ch_max_samples= samples;
00369 }
00370 offset+= p_header->m_fields.m_HEADER_0.m_fields.m_event_size<< 2;
00371 }
00372 }
00373 return TRUE;
00374 }
00376
00378 BOOL cvt_V1724_get_buffer_cache( cvt_V1724_data* p_data, UINT16 event_index, UINT8 ch_index, UINT16* p_buff, UINT32* p_buff_size, UINT8 *p_board_id, UINT32* p_trigger_time_tag, UINT32* p_event_counter)
00379 {
00380 CVT_V1724_HEADER *p_header;
00381 UINT32 offset= 0;
00382 UINT32 req_buff_size= *p_buff_size;
00383
00384 *p_buff_size= 0;
00385 *p_board_id= 0;
00386 *p_trigger_time_tag= 0;
00387 *p_event_counter= 0;
00388
00389
00390 do
00391 {
00392 p_header= (CVT_V1724_HEADER*)(( UINT8*)p_data->m_cache_sample_buffer+ offset);
00393 if( !event_index)
00394 {
00395 UINT8 ch_msk;
00396 int num_channels;
00397 int index;
00398 UINT32 i;
00399 UINT32 samples;
00400
00401 if( !( p_header->m_fields.m_HEADER_1.m_fields.m_active_channel_msk& ( 1<< ch_index)))
00402 {
00403
00404 return FALSE;
00405 }
00406
00407 for( ch_msk= 0x01, index= -1, i= 0, num_channels= 0; i< CVT_V1724_MAX_CHANNEL; ch_msk<<= 1, i++)
00408 {
00409 if( p_header->m_fields.m_HEADER_1.m_fields.m_active_channel_msk& ch_msk)
00410 {
00411 if( ch_msk== ( 1<< ch_index))
00412 {
00413
00414 index= num_channels;
00415 }
00416 ++num_channels;
00417 }
00418 }
00419 if( index< 0)
00420 {
00421 return FALSE;
00422 }
00423 samples= ((( p_header->m_fields.m_HEADER_0.m_fields.m_event_size<< 2)- sizeof( CVT_V1724_HEADER))/ num_channels)>> 1;
00424
00425
00426
00427 for( i= 0 ; ( i< samples)&& ( i< req_buff_size); i++)
00428 {
00429 p_buff[ i]= ((UINT16*)(( UINT8*)p_data->m_cache_sample_buffer+ offset+ sizeof( CVT_V1724_HEADER)))[ index* samples+ i]>> 2;
00430 }
00431 *p_buff_size= i;
00432 return TRUE;
00433 }
00434 offset+= p_header->m_fields.m_HEADER_0.m_fields.m_event_size<< 2;
00435 }
00436 while(( offset< p_data->m_cache_sample_buffer_read_bytes)&& ((int)( --event_index))>= 0 );
00437
00438 return FALSE;
00439 }
00440
00442
00444 BOOL cvt_V1724_set_trigger_mode( cvt_V1724_data* p_data, BOOL falling_edge_enable, BOOL trigger_in_enable, BOOL trigger_out_enable, BOOL ext_trigger_enable, BOOL sw_trigger_enable, UINT8 ch_trigger_enable_msk, BOOL trigger_overlap_enable, UINT32 post_trigger)
00445 {
00446 static const UINT32 CH_TRIGGER_MSK[ CVT_V1724_MAX_CHANNEL]=
00447 {
00448 CVT_V1724_TRGEN_CH0_MSK,
00449 CVT_V1724_TRGEN_CH1_MSK,
00450 CVT_V1724_TRGEN_CH2_MSK,
00451 CVT_V1724_TRGEN_CH3_MSK,
00452 CVT_V1724_TRGEN_CH4_MSK,
00453 CVT_V1724_TRGEN_CH5_MSK,
00454 CVT_V1724_TRGEN_CH6_MSK,
00455 CVT_V1724_TRGEN_CH7_MSK,
00456 };
00457
00458 UINT32 set_msk32= 0;
00459 UINT32 clear_msk32= 0;
00460
00461
00462
00463
00464
00465
00466 set_msk32|= ( !falling_edge_enable)? 0: CVT_V1724_BROAD_CHCTRL_TRG_OUT_THR_MSK;
00467 clear_msk32|= ( !falling_edge_enable)? CVT_V1724_BROAD_CHCTRL_TRG_OUT_THR_MSK: 0;
00468
00469
00470 set_msk32|= ( trigger_in_enable)? CVT_V1724_BROAD_CHCTRL_TRG_IN_EN_MSK: 0;
00471 clear_msk32|= ( trigger_in_enable)? 0: CVT_V1724_BROAD_CHCTRL_TRG_IN_EN_MSK;
00472
00473
00474 set_msk32|= ( trigger_out_enable)? CVT_V1724_BROAD_CHCTRL_TRG_OUT_EN_MSK: 0;
00475 clear_msk32|= ( trigger_out_enable)? 0: CVT_V1724_BROAD_CHCTRL_TRG_OUT_EN_MSK;
00476
00477
00478 set_msk32|= ( trigger_overlap_enable)? CVT_V1724_BROAD_CHCTRL_TRG_OVERLAP_MSK: 0;
00479 clear_msk32|= ( trigger_overlap_enable)? 0: CVT_V1724_BROAD_CHCTRL_TRG_OVERLAP_MSK;
00480
00481
00482
00483 if( set_msk32)
00484 {
00485 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_SET_CTRL_INDEX, &set_msk32))
00486 {
00487 TRACE( "V1724 BROADCAST CH CTRL write failed !\n");
00488 return FALSE;
00489 }
00490 }
00491 if( clear_msk32)
00492 {
00493 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_CLEAR_CTRL_INDEX, &clear_msk32))
00494 {
00495 TRACE( "V1724 BROADCAST CH CTRL write failed !\n");
00496 return FALSE;
00497 }
00498 }
00499
00500 set_msk32= 0;
00501 clear_msk32= 0;
00502
00503
00504
00505 set_msk32|= ( ext_trigger_enable)? CVT_V1724_TRGEN_EXT_MSK: 0;
00506 clear_msk32|= ( ext_trigger_enable)? 0: CVT_V1724_TRGEN_EXT_MSK;
00507
00508
00509 set_msk32|= ( sw_trigger_enable)? CVT_V1724_TRGEN_SW_MSK: 0;
00510 clear_msk32|= ( sw_trigger_enable)? 0: CVT_V1724_TRGEN_SW_MSK;
00511
00512
00513
00514 {
00515 int i;
00516 for( i= 0; i< CVT_V1724_MAX_CHANNEL ; i++, ch_trigger_enable_msk>>= 1)
00517 {
00518 if( ch_trigger_enable_msk& 0x01)
00519 {
00520 set_msk32|= CH_TRIGGER_MSK[ i];
00521 }
00522 else
00523 {
00524 clear_msk32|= CH_TRIGGER_MSK[ i];
00525 }
00526 }
00527 }
00528
00529
00530 if( set_msk32)
00531 {
00532 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1724_TRIGGER_SRC_ENABLE_INDEX, &set_msk32))
00533 {
00534 TRACE( "V1724 CVT_V1724_TRIGGER_SRC_ENABLE write failed !\n");
00535 return FALSE;
00536 }
00537 }
00538
00539
00540 if( clear_msk32)
00541 {
00542
00543 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1724_TRIGGER_SRC_ENABLE_INDEX, &clear_msk32))
00544 {
00545 TRACE( "V1724 CVT_V1724_TRIGGER_SRC_ENABLE write failed !\n");
00546 return FALSE;
00547 }
00548 }
00549
00550
00551
00552 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_POST_TRIG_INDEX, &post_trigger))
00553 {
00554 TRACE( "V1724 CVT_V1724_POST_TRIG write failed !\n");
00555 return FALSE;
00556 }
00557
00558 return TRUE;
00559 }
00560
00562
00564 BOOL cvt_V1724_get_trigger_mode( cvt_V1724_data* p_data, BOOL *p_falling_edge_enable, BOOL *p_trigger_in_enable, BOOL *p_trigger_out_enable, BOOL *p_ext_trigger_enable, BOOL *p_sw_trigger_enable, UINT8 *p_ch_trigger_enable_msk, BOOL *p_trigger_overlap_enable, UINT32 *p_post_trigger)
00565 {
00566 static const UINT32 CH_TRIGGER_MSK[ CVT_V1724_MAX_CHANNEL]=
00567 {
00568 CVT_V1724_TRGEN_CH0_MSK,
00569 CVT_V1724_TRGEN_CH1_MSK,
00570 CVT_V1724_TRGEN_CH2_MSK,
00571 CVT_V1724_TRGEN_CH3_MSK,
00572 CVT_V1724_TRGEN_CH4_MSK,
00573 CVT_V1724_TRGEN_CH5_MSK,
00574 CVT_V1724_TRGEN_CH6_MSK,
00575 CVT_V1724_TRGEN_CH7_MSK,
00576 };
00577
00578 UINT32 reg_value32= 0;
00579
00580
00581
00582 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_CTRL_INDEX, ®_value32))
00583 {
00584 TRACE( "V1724 BROADCAST CH CTRL read failed !\n");
00585 return FALSE;
00586 }
00587
00588
00589 *p_falling_edge_enable= ( reg_value32& CVT_V1724_BROAD_CHCTRL_TRG_OUT_THR_MSK) ? TRUE: FALSE;
00590
00591
00592 *p_trigger_in_enable= ( reg_value32& CVT_V1724_BROAD_CHCTRL_TRG_IN_EN_MSK) ? TRUE: FALSE;
00593
00594
00595 *p_trigger_out_enable= ( reg_value32& CVT_V1724_BROAD_CHCTRL_TRG_OUT_EN_MSK) ? TRUE: FALSE;
00596
00597
00598 *p_trigger_overlap_enable= ( reg_value32& CVT_V1724_BROAD_CHCTRL_TRG_OVERLAP_MSK) ? TRUE: FALSE;
00599
00600
00601
00602 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_TRIGGER_SRC_ENABLE_INDEX, ®_value32))
00603 {
00604 TRACE( "V1724 CVT_V1724_TRIGGER_SRC_ENABLE read failed !\n");
00605 return FALSE;
00606 }
00607
00608
00609 *p_ext_trigger_enable= ( reg_value32& CVT_V1724_TRGEN_EXT_MSK) ? TRUE: FALSE;
00610
00611
00612 *p_sw_trigger_enable= ( reg_value32& CVT_V1724_TRGEN_SW_MSK) ? TRUE: FALSE;
00613
00614
00615 {
00616 int i;
00617 int msk= 0x01;
00618 *p_ch_trigger_enable_msk= 0;
00619 for( i= 0; i< CVT_V1724_MAX_CHANNEL ; i++, msk<<= 1)
00620 {
00621 *p_ch_trigger_enable_msk|= ( reg_value32& CH_TRIGGER_MSK[ i])? msk: 0;
00622 }
00623 }
00624
00625
00626
00627
00628 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_POST_TRIG_INDEX, p_post_trigger))
00629 {
00630 TRACE( "V1724 CVT_V1724_POST_TRIG read failed !\n");
00631 return FALSE;
00632 }
00633
00634 return TRUE;
00635 }
00636
00638
00640 BOOL cvt_V1724_start_acquisition( cvt_V1724_data* p_data, UINT8 ch_msk)
00641 {
00642 UINT32 set_msk= 0;
00643 UINT32 reg_value32= 0;
00644
00645
00646
00647
00648
00649
00650
00651 reg_value32= ch_msk;
00652 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_CH_ENABLE_INDEX, ®_value32))
00653 {
00654 TRACE( "V1724 CHANNEL ENABLE write failed !\n");
00655 return FALSE;
00656 }
00657
00658
00659 set_msk|= CVT_V1724_ACQCTRL_START_MSK;
00660
00661 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1724_ACQ_CONTROL_INDEX, &set_msk))
00662 {
00663 TRACE( "V1724 ACQUISITION CONTROL write failed !\n");
00664 return FALSE;
00665 }
00666 return TRUE;
00667 }
00669
00671 BOOL cvt_V1724_stop_acquisition( cvt_V1724_data* p_data)
00672 {
00673 UINT32 clear_msk= 0;
00674
00675
00676 clear_msk|= CVT_V1724_ACQCTRL_START_MSK;
00677
00678 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1724_ACQ_CONTROL_INDEX, &clear_msk))
00679 {
00680 TRACE( "V1724 ACQUISITION CONTROL write failed !\n");
00681 return FALSE;
00682 }
00683 return TRUE;
00684 }
00686
00688 BOOL cvt_V1724_set_acquisition_mode( cvt_V1724_data* p_data, BOOL sample_enable, CVT_V1724_CH_BLKSIZE block_size, CVT_V1724_ACQ_CONTROL_ACQ_MODES acquisition_mode, BOOL count_all_trigger, UINT32 downsample_factor)
00689 {
00690 UINT32 set_msk= 0;
00691 UINT32 clear_msk= 0;
00692 UINT32 reg_value32;
00693
00694
00695
00696 switch( block_size)
00697 {
00698 case CVT_V1724_CHBKSZ_512:
00699 case CVT_V1724_CHBKSZ_1K:
00700 case CVT_V1724_CHBKSZ_2K:
00701 case CVT_V1724_CHBKSZ_4K:
00702 case CVT_V1724_CHBKSZ_8K:
00703 case CVT_V1724_CHBKSZ_16K:
00704 case CVT_V1724_CHBKSZ_32K:
00705 case CVT_V1724_CHBKSZ_64K:
00706 case CVT_V1724_CHBKSZ_128K:
00707 case CVT_V1724_CHBKSZ_256K:
00708 case CVT_V1724_CHBKSZ_512K:
00709 break;
00710 default:
00711 TRACE1( "V1724 Bad block size '%d'!\n", block_size);
00712 return FALSE;
00713 }
00714
00715
00716 set_msk|= ( sample_enable)? CVT_V1724_BROAD_CHCTRL_GATE_MODE_MSK: 0;
00717 clear_msk|= ( sample_enable)? 0: CVT_V1724_BROAD_CHCTRL_GATE_MODE_MSK;
00718
00719
00720
00721 if( set_msk)
00722 {
00723 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_SET_CTRL_INDEX, &set_msk))
00724 {
00725 TRACE( "V1724 CH SET CONTROL write failed !\n");
00726 return FALSE;
00727 }
00728 }
00729 if( clear_msk)
00730 {
00731 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_CLEAR_CTRL_INDEX, &clear_msk))
00732 {
00733 TRACE( "V1724 CH CLEAR CONTROL write failed !\n");
00734 return FALSE;
00735 }
00736 }
00737
00738
00739 reg_value32= block_size;
00740 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_BUFF_SIZE_INDEX, ®_value32))
00741 {
00742 TRACE( "V1724 CH BLOCK SIZE write failed !\n");
00743 return FALSE;
00744 }
00745
00746 reg_value32= 0;
00747 set_msk= 0;
00748 clear_msk= 0;
00749
00750 CVT_V1724_SET_ACQCTRL_ACQ_MODE( reg_value32, acquisition_mode);
00751 set_msk|= ( reg_value32& CVT_V1724_ACQCTRL_ACQ_MODE_MSK);
00752 clear_msk|= (( ~reg_value32)& CVT_V1724_ACQCTRL_ACQ_MODE_MSK);
00753
00754
00755 set_msk|= ( count_all_trigger)? CVT_V1724_ACQCTRL_EVENT_COUNTER_ALL_MSK: 0;
00756 clear_msk|= ( count_all_trigger)? 0: CVT_V1724_ACQCTRL_EVENT_COUNTER_ALL_MSK;
00757
00758
00759 set_msk|= ( downsample_factor)? CVT_V1724_ACQCTRL_DOWNSAMPLE_MSK: 0;
00760 clear_msk|= ( downsample_factor)? 0: CVT_V1724_ACQCTRL_DOWNSAMPLE_MSK;
00761
00762 if( set_msk)
00763 {
00764 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1724_ACQ_CONTROL_INDEX, &set_msk))
00765 {
00766 TRACE( "V1724 ACQUISITION CONTROL write failed !\n");
00767 return FALSE;
00768 }
00769 }
00770 if( clear_msk)
00771 {
00772 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1724_ACQ_CONTROL_INDEX, &clear_msk))
00773 {
00774 TRACE( "V1724 ACQUISITION CONTROL write failed !\n");
00775 return FALSE;
00776 }
00777 }
00778
00779 if( downsample_factor)
00780 {
00781 reg_value32= downsample_factor;
00782 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_DOWNSAMPLE_FACT_INDEX, ®_value32))
00783 {
00784 TRACE( "V1724 DOWNSAMPLE FACTOR write failed !\n");
00785 return FALSE;
00786 }
00787 }
00788 return TRUE;
00789 }
00790
00792
00794 BOOL cvt_V1724_get_acquisition_mode( cvt_V1724_data* p_data, BOOL *p_sample_enable, CVT_V1724_CH_BLKSIZE *p_block_size)
00795 {
00796 UINT32 reg_value32= 0;
00797
00798
00799
00800 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_CTRL_INDEX, ®_value32))
00801 {
00802 TRACE( "CVT_V1724_BROAD_CH_CTRL read failed !\n");
00803 return FALSE;
00804 }
00805
00806
00807 *p_sample_enable= ( reg_value32& CVT_V1724_BROAD_CHCTRL_GATE_MODE_MSK)? TRUE: FALSE;
00808
00809
00810
00811 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_BUFF_SIZE_INDEX, ®_value32))
00812 {
00813 TRACE( "CVT_V1724_BROAD_CH_BUFF_SIZE read failed !\n");
00814 return FALSE;
00815 }
00816 *p_block_size= reg_value32;
00817 return TRUE;
00818 }
00819
00821
00823 BOOL cvt_V1724_get_acquisition_status( cvt_V1724_data* p_data, BOOL *p_is_MEB_not_empty, BOOL *p_is_MEB_full, BOOL *p_is_running, BOOL *p_some_event_ready, BOOL *p_event_full, BOOL *p_s_in)
00824 {
00825 UINT32 reg_value32= 0;
00826
00827
00828
00829 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ACQ_STATUS_INDEX, ®_value32))
00830 {
00831 TRACE( "V1724 ACQUISITION STATUS read failed !\n");
00832 return FALSE;
00833 }
00834
00835
00836
00837 *p_is_MEB_not_empty= ( reg_value32& CVT_V1724_ACQSTS_MEB_NOT_EMPTY_MSK)? TRUE: FALSE;
00838
00839
00840
00841 *p_is_MEB_full= ( reg_value32& CVT_V1724_ACQSTS_MEB_FULL_MSK)? TRUE: FALSE;
00842
00843
00844
00845 *p_is_running= ( reg_value32& CVT_V1724_ACQSTS_RUN_MSK)? TRUE: FALSE;
00846
00847
00848
00849 *p_some_event_ready= ( reg_value32& CVT_V1724_ACQSTS_EVENT_RDY_MSK)? TRUE: FALSE;
00850
00851
00852
00853 *p_event_full= ( reg_value32& CVT_V1724_ACQSTS_EVENT_FULL_MSK)? TRUE: FALSE;
00854
00855
00856
00857 *p_s_in= ( reg_value32& CVT_V1724_ACQSTS_S_IN_MSK)? TRUE: FALSE;
00858
00859 return TRUE;
00860 }
00861
00863
00865 BOOL cvt_V1724_set_fp_trigger_out( cvt_V1724_data* p_data, BOOL ext_trigger_enable, BOOL sw_trigger_enable, UINT8 ch_trigger_enable_msk)
00866 {
00867 static const UINT32 CH_TRIGGER_MSK[ CVT_V1724_MAX_CHANNEL]=
00868 {
00869 CVT_V1724_FPTRGEN_CH0_MSK,
00870 CVT_V1724_FPTRGEN_CH1_MSK,
00871 CVT_V1724_FPTRGEN_CH2_MSK,
00872 CVT_V1724_FPTRGEN_CH3_MSK,
00873 CVT_V1724_FPTRGEN_CH4_MSK,
00874 CVT_V1724_FPTRGEN_CH5_MSK,
00875 CVT_V1724_FPTRGEN_CH6_MSK,
00876 CVT_V1724_FPTRGEN_CH7_MSK,
00877 };
00878
00879 UINT32 set_msk32= 0;
00880 UINT32 clear_msk32= 0;
00881
00882
00883
00884 set_msk32|= ( ext_trigger_enable)? CVT_V1724_FPTRGEN_EXT_MSK: 0;
00885 clear_msk32|= ( ext_trigger_enable)? 0: CVT_V1724_FPTRGEN_EXT_MSK;
00886
00887
00888 set_msk32|= ( sw_trigger_enable)? CVT_V1724_FPTRGEN_SW_MSK: 0;
00889 clear_msk32|= ( sw_trigger_enable)? 0: CVT_V1724_FPTRGEN_SW_MSK;
00890
00891
00892
00893 {
00894 int i;
00895 for( i= 0; i< CVT_V1724_MAX_CHANNEL ; i++, ch_trigger_enable_msk>>= 1)
00896 {
00897 if( ch_trigger_enable_msk& 0x01)
00898 {
00899 set_msk32|= CH_TRIGGER_MSK[ i];
00900 }
00901 else
00902 {
00903 clear_msk32|= CH_TRIGGER_MSK[ i];
00904 }
00905 }
00906 }
00907
00908
00909 if( set_msk32)
00910 {
00911 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1724_FP_TRIGGER_OUT_ENABLE_INDEX, &set_msk32))
00912 {
00913 TRACE( "V1724 CVT_V1724_TRIGGER_SRC_ENABLE write failed !\n");
00914 return FALSE;
00915 }
00916 }
00917
00918
00919 if( clear_msk32)
00920 {
00921
00922 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1724_FP_TRIGGER_OUT_ENABLE_INDEX, &clear_msk32))
00923 {
00924 TRACE( "V1724 CVT_V1724_TRIGGER_SRC_ENABLE write failed !\n");
00925 return FALSE;
00926 }
00927 }
00928
00929 return TRUE;
00930 }
00932
00934 BOOL cvt_V1724_get_fp_trigger_out( cvt_V1724_data* p_data, BOOL *p_ext_trigger_enable, BOOL *p_sw_trigger_enable, UINT8 *p_ch_trigger_enable_msk)
00935 {
00936 static const UINT32 CH_TRIGGER_MSK[ CVT_V1724_MAX_CHANNEL]=
00937 {
00938 CVT_V1724_FPTRGEN_CH0_MSK,
00939 CVT_V1724_FPTRGEN_CH1_MSK,
00940 CVT_V1724_FPTRGEN_CH2_MSK,
00941 CVT_V1724_FPTRGEN_CH3_MSK,
00942 CVT_V1724_FPTRGEN_CH4_MSK,
00943 CVT_V1724_FPTRGEN_CH5_MSK,
00944 CVT_V1724_FPTRGEN_CH6_MSK,
00945 CVT_V1724_FPTRGEN_CH7_MSK,
00946 };
00947
00948 UINT32 reg_value32= 0;
00949
00950
00951
00952 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_FP_TRIGGER_OUT_ENABLE_INDEX, ®_value32))
00953 {
00954 TRACE( "V1724 CVT_V1724_FP_TRIGGER_OUT_ENABLE read failed !\n");
00955 return FALSE;
00956 }
00957
00958
00959 *p_ext_trigger_enable= ( reg_value32& CVT_V1724_FPTRGEN_EXT_MSK) ? TRUE: FALSE;
00960
00961
00962 *p_sw_trigger_enable= ( reg_value32& CVT_V1724_FPTRGEN_SW_MSK) ? TRUE: FALSE;
00963
00964
00965 {
00966 int i;
00967 int msk= 0x01;
00968 *p_ch_trigger_enable_msk= 0;
00969 for( i= 0; i< CVT_V1724_MAX_CHANNEL ; i++, msk<<= 1)
00970 {
00971 *p_ch_trigger_enable_msk|= ( reg_value32& CH_TRIGGER_MSK[ i])? msk: 0;
00972 }
00973 }
00974
00975 return TRUE;
00976 }
00977
00979
00981 BOOL cvt_V1724_set_dither_enable( cvt_V1724_data* p_data, UINT8 ch_msk, BOOL dither_value)
00982 {
00983 static const UINT16 CH_CONF[ CVT_V1724_MAX_CHANNEL]=
00984 {
00985 CVT_V1724_CH0_ADC_CONF_INDEX,
00986 CVT_V1724_CH1_ADC_CONF_INDEX,
00987 CVT_V1724_CH2_ADC_CONF_INDEX,
00988 CVT_V1724_CH3_ADC_CONF_INDEX,
00989 CVT_V1724_CH4_ADC_CONF_INDEX,
00990 CVT_V1724_CH5_ADC_CONF_INDEX,
00991 CVT_V1724_CH6_ADC_CONF_INDEX,
00992 CVT_V1724_CH7_ADC_CONF_INDEX,
00993 };
00994 UINT32 set_msk= 0;
00995
00996
00997 set_msk|= CVT_V1724_CHCONF_DITHER_MSK;
00998
00999 if( dither_value)
01000 {
01001 int i;
01002 for( i= 0; (i< CVT_V1724_MAX_CHANNEL )&& ch_msk; i++, ch_msk>>= 1)
01003 {
01004 if( !(ch_msk& 0x01))
01005 continue;
01006 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CH_CONF[ i], &set_msk))
01007 {
01008 TRACE( "V1724 CH CONF write failed !\n");
01009 return FALSE;
01010 }
01011 }
01012 }
01013 else
01014 {
01015 int i;
01016 for( i= 0; (i< CVT_V1724_MAX_CHANNEL )&& ch_msk; i++, ch_msk>>= 1)
01017 {
01018 if( !(ch_msk& 0x01))
01019 continue;
01020 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CH_CONF[ i], &set_msk))
01021 {
01022 TRACE( "V1724 CH CONF write failed !\n");
01023 return FALSE;
01024 }
01025 }
01026 }
01027 return TRUE;
01028 }
01029
01031
01033 BOOL cvt_V1724_get_dither_enable( cvt_V1724_data* p_data, UINT8 ch_index, BOOL *p_dither_value)
01034 {
01035 static const UINT16 CH_CONF[ CVT_V1724_MAX_CHANNEL]=
01036 {
01037 CVT_V1724_CH0_ADC_CONF_INDEX,
01038 CVT_V1724_CH1_ADC_CONF_INDEX,
01039 CVT_V1724_CH2_ADC_CONF_INDEX,
01040 CVT_V1724_CH3_ADC_CONF_INDEX,
01041 CVT_V1724_CH4_ADC_CONF_INDEX,
01042 CVT_V1724_CH5_ADC_CONF_INDEX,
01043 CVT_V1724_CH6_ADC_CONF_INDEX,
01044 CVT_V1724_CH7_ADC_CONF_INDEX,
01045 };
01046 UINT32 reg_value32= 0;
01047
01048
01049
01050 if( ch_index>= CVT_V1724_MAX_CHANNEL)
01051 {
01052 TRACE1( "V1724 cvt_V1724_get_dither_enable bad channel '%d'!\n", ch_index);
01053 return FALSE;
01054 }
01055
01056
01057
01058 if( !cvt_read_reg( &p_data->m_common_data, CH_CONF[ ch_index], ®_value32))
01059 {
01060 TRACE( "V1724 CH CONF read failed !\n");
01061 return FALSE;
01062 }
01063
01064
01065
01066 *p_dither_value= ( reg_value32& CVT_V1724_CHCONF_DITHER_MSK)? TRUE: FALSE;
01067
01068 return TRUE;
01069 }
01070
01072
01074 BOOL cvt_V1724_set_adc_conf( cvt_V1724_data* p_data, UINT8 ch_msk, BOOL dither_value, BOOL clk_duty_stab_value, BOOL randomize_value)
01075 {
01076 static const UINT16 CH_CONF[ CVT_V1724_MAX_CHANNEL]=
01077 {
01078 CVT_V1724_CH0_ADC_CONF_INDEX,
01079 CVT_V1724_CH1_ADC_CONF_INDEX,
01080 CVT_V1724_CH2_ADC_CONF_INDEX,
01081 CVT_V1724_CH3_ADC_CONF_INDEX,
01082 CVT_V1724_CH4_ADC_CONF_INDEX,
01083 CVT_V1724_CH5_ADC_CONF_INDEX,
01084 CVT_V1724_CH6_ADC_CONF_INDEX,
01085 CVT_V1724_CH7_ADC_CONF_INDEX,
01086 };
01087 UINT32 set_msk32= 0;
01088 UINT32 clear_msk32= 0;
01089
01090
01091 set_msk32|= ( dither_value)? CVT_V1724_CHCONF_DITHER_MSK: 0;
01092 clear_msk32|= ( dither_value)? 0: CVT_V1724_CHCONF_DITHER_MSK;
01093
01094
01095 set_msk32|= ( clk_duty_stab_value)? CVT_V1724_CHCONF_CLK_DUTY_STAB_MSK: 0;
01096 clear_msk32|= ( clk_duty_stab_value)? 0: CVT_V1724_CHCONF_CLK_DUTY_STAB_MSK;
01097
01098
01099 set_msk32|= ( randomize_value)? CVT_V1724_CHCONF_RND_MSK: 0;
01100 clear_msk32|= ( randomize_value)? 0: CVT_V1724_CHCONF_RND_MSK;
01101
01102
01103
01104 if( set_msk32)
01105 {
01106 int i;
01107 UINT8 act_ch_msk= ch_msk;
01108 for( i= 0; (i< CVT_V1724_MAX_CHANNEL )&& act_ch_msk; i++, act_ch_msk>>= 1)
01109 {
01110 if( !( act_ch_msk& 0x01))
01111 continue;
01112 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CH_CONF[ i], &set_msk32))
01113 {
01114 TRACE( "V1724 CH CONF write failed !\n");
01115 return FALSE;
01116 }
01117 }
01118 }
01119
01120
01121 if( clear_msk32)
01122 {
01123 int i;
01124 UINT8 act_ch_msk= ch_msk;
01125 for( i= 0; (i< CVT_V1724_MAX_CHANNEL )&& act_ch_msk; i++, act_ch_msk>>= 1)
01126 {
01127 if( !( act_ch_msk& 0x01))
01128 continue;
01129 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CH_CONF[ i], &clear_msk32))
01130 {
01131 TRACE( "V1724 CH CONF write failed !\n");
01132 return FALSE;
01133 }
01134 }
01135 }
01136 return TRUE;
01137 }
01138
01140
01142 BOOL cvt_V1724_get_adc_conf( cvt_V1724_data* p_data, UINT8 ch_index, BOOL *p_dither_value, BOOL *p_clk_duty_stab_value, BOOL *p_randomize_value)
01143 {
01144 static const UINT16 CH_CONF[ CVT_V1724_MAX_CHANNEL]=
01145 {
01146 CVT_V1724_CH0_ADC_CONF_INDEX,
01147 CVT_V1724_CH1_ADC_CONF_INDEX,
01148 CVT_V1724_CH2_ADC_CONF_INDEX,
01149 CVT_V1724_CH3_ADC_CONF_INDEX,
01150 CVT_V1724_CH4_ADC_CONF_INDEX,
01151 CVT_V1724_CH5_ADC_CONF_INDEX,
01152 CVT_V1724_CH6_ADC_CONF_INDEX,
01153 CVT_V1724_CH7_ADC_CONF_INDEX,
01154 };
01155 UINT32 reg_value32= 0;
01156
01157
01158
01159 if( ch_index>= CVT_V1724_MAX_CHANNEL)
01160 {
01161 TRACE1( "V1724 cvt_V1724_get_dither_enable bad channel '%d'!\n", ch_index);
01162 return FALSE;
01163 }
01164
01165
01166
01167 if( !cvt_read_reg( &p_data->m_common_data, CH_CONF[ ch_index], ®_value32))
01168 {
01169 TRACE( "V1724 CH CONF read failed !\n");
01170 return FALSE;
01171 }
01172
01173
01174
01175 *p_dither_value= ( reg_value32& CVT_V1724_CHCONF_DITHER_MSK)? TRUE: FALSE;
01176
01177
01178 *p_clk_duty_stab_value= ( reg_value32& CVT_V1724_CHCONF_CLK_DUTY_STAB_MSK)? TRUE: FALSE;
01179
01180
01181 *p_randomize_value= ( reg_value32& CVT_V1724_CHCONF_RND_MSK)? TRUE: FALSE;
01182
01183 return TRUE;
01184 }
01185
01187
01189 BOOL cvt_V1724_set_interrupt( cvt_V1724_data* p_data, UINT8 level, UINT32 status_id, UINT16 event_number)
01190 {
01191 UINT32 reg_value;
01192
01193
01194 reg_value= level& 0x07;
01195 if( level!= reg_value)
01196 {
01197 TRACE( "V1724 bad interrupt level !\n");
01198 return FALSE;
01199 }
01200 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_VME_CONTROL_INDEX, ®_value))
01201 {
01202 TRACE( "V1724 CVT_V1724_VME_CONTROL read failed !\n");
01203 return FALSE;
01204 }
01205 CVT_V1724_SET_INT_LEVEL( reg_value, level);
01206 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_VME_CONTROL_INDEX, ®_value))
01207 {
01208 TRACE( "V1724 CVT_V1724_VME_CONTROL write failed !\n");
01209 return FALSE;
01210 }
01211
01212
01213
01214 reg_value= event_number& 0x03ff;
01215 if( event_number!= reg_value)
01216 {
01217 TRACE( "V1724 bad event number !\n");
01218 return FALSE;
01219 }
01220 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_INT_EVENT_NUM_INDEX, ®_value))
01221 {
01222 TRACE( "V1724 CVT_V1724_INT_EVENT_NUM write failed !\n");
01223 return FALSE;
01224 }
01225
01226
01227 reg_value= status_id;
01228 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_INT_STATUS_ID_INDEX, ®_value))
01229 {
01230 TRACE( "V1724 CVT_V1724_INT_STATUS_ID write failed !\n");
01231 return FALSE;
01232 }
01233
01234 return TRUE;
01235 }
01236
01238
01240 BOOL cvt_V1724_get_interrupt( cvt_V1724_data* p_data, UINT8 *p_level, UINT32 *p_status_id, UINT16 *p_event_number)
01241 {
01242 UINT32 reg_value32;
01243
01244
01245 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_VME_CONTROL_INDEX, ®_value32))
01246 {
01247 TRACE( "V1724 CVT_V1724_VME_CONTROL read failed !\n");
01248 return FALSE;
01249 }
01250
01251
01252 *p_level= CVT_V1724_GET_INT_LEVEL( reg_value32);
01253
01254
01255
01256 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_INT_EVENT_NUM_INDEX, ®_value32))
01257 {
01258 TRACE( "V1724 CVT_V1724_INT_EVENT_NUM read failed !\n");
01259 return FALSE;
01260 }
01261 *p_event_number= reg_value32& 0x03ff;
01262
01263
01264
01265 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_INT_STATUS_ID_INDEX, ®_value32))
01266 {
01267 TRACE( "V1724 CVT_V1724_INT_STATUS_ID read failed !\n");
01268 return FALSE;
01269 }
01270
01271
01272 *p_status_id= ( UINT8)reg_value32;
01273
01274 return TRUE;
01275 }
01276
01278
01280 BOOL cvt_V1724_set_readout_mode( cvt_V1724_data* p_data, BOOL enable_bus_error, UINT32 BLT_event_number)
01281 {
01282 UINT32 set_msk= 0;
01283 UINT32 clear_msk= 0;
01284
01285
01286
01287 set_msk|= ( enable_bus_error)? CVT_V1724_VME_CTRL_BERR_ENABLE_MSK: 0;
01288 clear_msk|= ( enable_bus_error)? 0: CVT_V1724_VME_CTRL_BERR_ENABLE_MSK;
01289
01290
01291
01292 if( set_msk)
01293 {
01294 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1724_VME_CONTROL_INDEX, &set_msk))
01295 {
01296 TRACE( "V1724 CVT_V1724_VME_CONTROL write failed !\n");
01297 return FALSE;
01298 }
01299 }
01300
01301
01302 if( clear_msk)
01303 {
01304
01305 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1724_VME_CONTROL_INDEX, &clear_msk))
01306 {
01307 TRACE( "V1724 CVT_V1724_CONTROL write failed !\n");
01308 return FALSE;
01309 }
01310 }
01311
01312
01313
01314 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BLT_EVENT_NUM_INDEX, &BLT_event_number))
01315 {
01316 TRACE( "V1724 CVT_V1724_BLT_EVENT_NUM write failed !\n");
01317 return FALSE;
01318 }
01319
01320 return TRUE;
01321 }
01322
01324
01326 BOOL cvt_V1724_get_readout_mode( cvt_V1724_data* p_data, BOOL *p_enable_bus_error, UINT32 *p_BLT_event_number)
01327 {
01328 UINT32 reg_value32= 0;
01329
01330
01331
01332 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_VME_CONTROL_INDEX, ®_value32))
01333 {
01334 TRACE( "V1724 CVT_V1724_VME_CONTROL read failed !\n");
01335 return FALSE;
01336 }
01337
01338
01339 *p_enable_bus_error= ( reg_value32& CVT_V1724_VME_CTRL_BERR_ENABLE_MSK)? TRUE: FALSE;
01340
01341
01342
01343 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_BLT_EVENT_NUM_INDEX, p_BLT_event_number))
01344 {
01345 TRACE( "V1724 CVT_V1724_BLT_EVENT_NUM read failed !\n");
01346 return FALSE;
01347 }
01348
01349 return TRUE;
01350 }
01351
01353
01355 BOOL cvt_V1724_software_reset( cvt_V1724_data* p_data)
01356 {
01357
01358
01359 UINT32 reg_value= 0;
01360 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_SW_RESET_INDEX, ®_value))
01361 {
01362 TRACE( "V1724 CVT_V1724_SW_RESET write failed !\n");
01363 return FALSE;
01364 }
01365 return TRUE;
01366 }
01367
01369
01371 BOOL cvt_V1724_data_clear( cvt_V1724_data* p_data)
01372 {
01373
01374
01375 UINT32 reg_value= 0;
01376 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_SW_CLEAR_INDEX, ®_value))
01377 {
01378 TRACE( "V1724 CVT_V1724_CLEAR_RESET write failed !\n");
01379 return FALSE;
01380 }
01381 return TRUE;
01382 }
01383
01385
01387 BOOL cvt_V1724_set_channel_offset( cvt_V1724_data* p_data, UINT8 ch_msk, UINT16 offset_value)
01388 {
01389 static const UINT16 CH_DAC_CONF[ CVT_V1724_MAX_CHANNEL]=
01390 {
01391 CVT_V1724_CH0_DAC_CONF_INDEX,
01392 CVT_V1724_CH1_DAC_CONF_INDEX,
01393 CVT_V1724_CH2_DAC_CONF_INDEX,
01394 CVT_V1724_CH3_DAC_CONF_INDEX,
01395 CVT_V1724_CH4_DAC_CONF_INDEX,
01396 CVT_V1724_CH5_DAC_CONF_INDEX,
01397 CVT_V1724_CH6_DAC_CONF_INDEX,
01398 CVT_V1724_CH7_DAC_CONF_INDEX,
01399 };
01400 UINT32 reg_value_A= 0, reg_value_B= 0;
01401
01402
01403
01404
01405
01406 CVT_V1724_SET_CH_DAC_CONF( reg_value_A, offset_value);
01407 reg_value_A|= CVT_V1724_CHDAC_SET_A_MSK;
01408
01409
01410 CVT_V1724_SET_CH_DAC_CONF( reg_value_B, offset_value);
01411 reg_value_B|= CVT_V1724_CHDAC_SET_B_MSK;
01412
01413
01414
01415 {
01416 int i;
01417 for( i= 0; (i< CVT_V1724_MAX_CHANNEL )&& ch_msk; i++, ch_msk>>= 1)
01418 {
01419 if( ch_msk& 0x01)
01420 {
01421
01422
01423 BOOL trash;
01424 BOOL is_dac_busy= TRUE;
01425 while( is_dac_busy)
01426 {
01427
01428
01429 if( !cvt_V1724_get_channel_status( p_data, i, &is_dac_busy, &trash, &trash, &trash))
01430 {
01431 TRACE( "V1724 set channel offset failed !\n");
01432 return FALSE;
01433 }
01434 }
01435 if( !cvt_write_reg( &p_data->m_common_data, CH_DAC_CONF[ i], ( i& 0x01)? ®_value_B: ®_value_A))
01436 {
01437 TRACE( "V1724 CH DAC CONF write failed !\n");
01438 return FALSE;
01439 }
01440 }
01441 }
01442 }
01443
01444 return TRUE;
01445 }
01447
01449 BOOL cvt_V1724_get_channel_offset( cvt_V1724_data* p_data, UINT8 ch_index, UINT16 *p_offset_value)
01450 {
01451 static const UINT16 CH_DAC_CONF[ CVT_V1724_MAX_CHANNEL]=
01452 {
01453 CVT_V1724_CH0_DAC_CONF_INDEX,
01454 CVT_V1724_CH1_DAC_CONF_INDEX,
01455 CVT_V1724_CH2_DAC_CONF_INDEX,
01456 CVT_V1724_CH3_DAC_CONF_INDEX,
01457 CVT_V1724_CH4_DAC_CONF_INDEX,
01458 CVT_V1724_CH5_DAC_CONF_INDEX,
01459 CVT_V1724_CH6_DAC_CONF_INDEX,
01460 CVT_V1724_CH7_DAC_CONF_INDEX,
01461 };
01462 UINT32 reg_value32= 0;
01463 BOOL trash;
01464 BOOL is_dac_busy= TRUE;
01465
01466
01467
01468 if( ch_index>= CVT_V1724_MAX_CHANNEL)
01469 {
01470 TRACE1( "V1724 cvt_V1724_get_channel_offset bad channel '%d'!\n", ch_index);
01471 return FALSE;
01472 }
01473
01474
01475
01476 while( is_dac_busy)
01477 {
01478
01479 if( !cvt_V1724_get_channel_status( p_data, ch_index, &is_dac_busy, &trash, &trash, &trash))
01480 {
01481 TRACE( "V1724 set channel offset failed !\n");
01482 return FALSE;
01483 }
01484 }
01485
01486
01487 if( !cvt_read_reg( &p_data->m_common_data, CH_DAC_CONF[ ch_index], ®_value32))
01488 {
01489 TRACE( "V1724 CH DAC CONF read failed !\n");
01490 return FALSE;
01491 }
01492
01493
01494 *p_offset_value= CVT_V1724_GET_CH_DAC_CONF( reg_value32);
01495
01496 return TRUE;
01497 }
01498
01499
01501
01503 BOOL cvt_V1724_set_channel_trigger( cvt_V1724_data* p_data, UINT8 ch_msk, UINT32 trigger_threshold, UINT32 threshold_samples)
01504 {
01505 static const UINT16 CH_TRG_THR[ CVT_V1724_MAX_CHANNEL]=
01506 {
01507 CVT_V1724_CH0_THRESHOLD_INDEX,
01508 CVT_V1724_CH1_THRESHOLD_INDEX,
01509 CVT_V1724_CH2_THRESHOLD_INDEX,
01510 CVT_V1724_CH3_THRESHOLD_INDEX,
01511 CVT_V1724_CH4_THRESHOLD_INDEX,
01512 CVT_V1724_CH5_THRESHOLD_INDEX,
01513 CVT_V1724_CH6_THRESHOLD_INDEX,
01514 CVT_V1724_CH7_THRESHOLD_INDEX,
01515 };
01516
01517 static const UINT16 CH_TRG_THR_SAMPLE[ CVT_V1724_MAX_CHANNEL]=
01518 {
01519 CVT_V1724_CH0_TIME_OVER_UNDER_THR_INDEX,
01520 CVT_V1724_CH1_TIME_OVER_UNDER_THR_INDEX,
01521 CVT_V1724_CH2_TIME_OVER_UNDER_THR_INDEX,
01522 CVT_V1724_CH3_TIME_OVER_UNDER_THR_INDEX,
01523 CVT_V1724_CH4_TIME_OVER_UNDER_THR_INDEX,
01524 CVT_V1724_CH5_TIME_OVER_UNDER_THR_INDEX,
01525 CVT_V1724_CH6_TIME_OVER_UNDER_THR_INDEX,
01526 CVT_V1724_CH7_TIME_OVER_UNDER_THR_INDEX,
01527 };
01528
01529
01530
01531 {
01532 int i;
01533 UINT8 tmp_msk= ch_msk;
01534 UINT32 reg_value= trigger_threshold;
01535 for( i= 0; (i< CVT_V1724_MAX_CHANNEL )&& tmp_msk; i++, tmp_msk>>= 1)
01536 {
01537 if( tmp_msk& 0x01)
01538 {
01539 if( !cvt_write_reg( &p_data->m_common_data, CH_TRG_THR[ i], ®_value))
01540 {
01541 TRACE( "V1724 CH TRIGGER THRESHOLD write failed !\n");
01542 return FALSE;
01543 }
01544 }
01545 }
01546 }
01547
01548
01549
01550 {
01551 int i;
01552 UINT8 tmp_msk= ch_msk;
01553 UINT32 reg_value= threshold_samples;
01554 for( i= 0; (i< CVT_V1724_MAX_CHANNEL)&& tmp_msk; i++, tmp_msk>>= 1)
01555 {
01556 if( tmp_msk& 0x01)
01557 {
01558 if( !cvt_write_reg( &p_data->m_common_data, CH_TRG_THR_SAMPLE[ i], ®_value))
01559 {
01560 TRACE( "V1724 CH TRIGGER THRESHOLD SAMPLES write failed !\n");
01561 return FALSE;
01562 }
01563 }
01564 }
01565 }
01566 return TRUE;
01567 }
01569
01571 BOOL cvt_V1724_get_channel_trigger( cvt_V1724_data* p_data, UINT8 ch_index, UINT32 *p_trigger_threshold, UINT32 *p_threshold_samples)
01572 {
01573 static const UINT16 CH_TRG_THR[ CVT_V1724_MAX_CHANNEL]=
01574 {
01575 CVT_V1724_CH0_THRESHOLD_INDEX,
01576 CVT_V1724_CH1_THRESHOLD_INDEX,
01577 CVT_V1724_CH2_THRESHOLD_INDEX,
01578 CVT_V1724_CH3_THRESHOLD_INDEX,
01579 CVT_V1724_CH4_THRESHOLD_INDEX,
01580 CVT_V1724_CH5_THRESHOLD_INDEX,
01581 CVT_V1724_CH6_THRESHOLD_INDEX,
01582 CVT_V1724_CH7_THRESHOLD_INDEX,
01583 };
01584
01585 static const UINT16 CH_TRG_THR_SAMPLE[ CVT_V1724_MAX_CHANNEL]=
01586 {
01587 CVT_V1724_CH0_TIME_OVER_UNDER_THR_INDEX,
01588 CVT_V1724_CH1_TIME_OVER_UNDER_THR_INDEX,
01589 CVT_V1724_CH2_TIME_OVER_UNDER_THR_INDEX,
01590 CVT_V1724_CH3_TIME_OVER_UNDER_THR_INDEX,
01591 CVT_V1724_CH4_TIME_OVER_UNDER_THR_INDEX,
01592 CVT_V1724_CH5_TIME_OVER_UNDER_THR_INDEX,
01593 CVT_V1724_CH6_TIME_OVER_UNDER_THR_INDEX,
01594 CVT_V1724_CH7_TIME_OVER_UNDER_THR_INDEX,
01595 };
01596
01597
01598
01599 if( ch_index>= CVT_V1724_MAX_CHANNEL)
01600 {
01601 TRACE1( "V1724 cvt_V1724_get_channel_trigger bad channel '%d'!\n", ch_index);
01602 return FALSE;
01603 }
01604
01605
01606
01607 if( !cvt_read_reg( &p_data->m_common_data, CH_TRG_THR[ ch_index], p_trigger_threshold))
01608 {
01609 TRACE( "V1724 CH TRIGGER THRESHOLD read failed !\n");
01610 return FALSE;
01611 }
01612
01613
01614
01615 if( !cvt_read_reg( &p_data->m_common_data, CH_TRG_THR_SAMPLE[ ch_index], p_threshold_samples))
01616 {
01617 TRACE( "V1724 CH TRIGGER THRESHOLD SAMPLES read failed !\n");
01618 return FALSE;
01619 }
01620
01621 return TRUE;
01622 }
01623
01625
01627 BOOL cvt_V1724_set_front_panel_IO( cvt_V1724_data* p_data, BOOL use_TTL, BOOL out_en, UINT8 dir_msk, CVT_V1724_FRONT_PANEL_IO_MODES mode)
01628 {
01629 UINT32 reg_value32= 0;
01630
01631
01632
01633 switch( mode)
01634 {
01635 case CVT_V1724_FPIO_MODES_GPIO:
01636 case CVT_V1724_FPIO_MODES_PROGIO:
01637 case CVT_V1724_FPIO_MODES_PATTERN:
01638 break;
01639 default:
01640 TRACE( "V1724 CVT_V1724_FRONT_PANEL_IO_CTRL bad mode !\n");
01641 return FALSE;
01642 }
01643
01644
01645
01646 reg_value32|= ( use_TTL)? CVT_V1724_FPIO_CTRL_TTL_MSK: 0;
01647
01648
01649
01650 reg_value32|= ( out_en)? 0: CVT_V1724_FPIO_CTRL_OUT_DIS_MSK;
01651
01652
01653
01654 CVT_V1724_SET_FPIO_CTRL_DIR( reg_value32, dir_msk);
01655
01656
01657
01658 CVT_V1724_SET_FPIO_CTRL_MODE( reg_value32, mode);
01659
01660 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FRONT_PANEL_IO_CTRL_INDEX, ®_value32))
01661 {
01662 TRACE( "V1724 CVT_V1724_FRONT_PANEL_IO_CTRL write failed !\n");
01663 return FALSE;
01664 }
01665 return TRUE;
01666 }
01667
01669
01671 BOOL cvt_V1724_get_front_panel_IO( cvt_V1724_data* p_data, BOOL *p_use_TTL, BOOL *p_is_out_en, UINT8 *p_dir_msk, CVT_V1724_FRONT_PANEL_IO_MODES *p_mode)
01672 {
01673 UINT32 reg_value32= 0;
01674
01675
01676
01677 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_FRONT_PANEL_IO_CTRL_INDEX, ®_value32))
01678 {
01679 TRACE( "V1724 CVT_V1724_FRONT_PANEL_IO_CTRL read failed !\n");
01680 return FALSE;
01681 }
01682
01683
01684 *p_use_TTL= ( reg_value32& CVT_V1724_FPIO_CTRL_TTL_MSK)? TRUE: FALSE;
01685
01686
01687
01688
01689 *p_is_out_en= ( reg_value32& CVT_V1724_FPIO_CTRL_OUT_DIS_MSK)? FALSE: TRUE;
01690
01691
01692
01693 *p_dir_msk= CVT_V1724_GET_FPIO_CTRL_DIR( reg_value32);
01694
01695
01696
01697 *p_mode= CVT_V1724_GET_FPIO_CTRL_MODE( reg_value32);
01698
01699 return TRUE;
01700 }
01701
01703
01705 BOOL cvt_V1724_software_trigger( cvt_V1724_data* p_data)
01706 {
01707 UINT32 reg_value;
01708
01709
01710 reg_value= 1;
01711 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_SW_TRIGGER_INDEX, ®_value))
01712 {
01713 TRACE( "V1724 CVT_V1724_SW_TRIGGER write failed !\n");
01714 return FALSE;
01715 }
01716 return TRUE;
01717 }
01718
01719
01721
01723 BOOL cvt_V1724_get_channel_status( cvt_V1724_data* p_data, UINT8 ch_index, BOOL *p_is_dac_busy, BOOL *p_is_fifo_full, BOOL *p_is_fifo_empty, BOOL *p_is_block_remove_ok)
01724 {
01725 static const UINT16 CH_STATUS[ CVT_V1724_MAX_CHANNEL]=
01726 {
01727 CVT_V1724_CH0_STATUS_INDEX,
01728 CVT_V1724_CH1_STATUS_INDEX,
01729 CVT_V1724_CH2_STATUS_INDEX,
01730 CVT_V1724_CH3_STATUS_INDEX,
01731 CVT_V1724_CH4_STATUS_INDEX,
01732 CVT_V1724_CH5_STATUS_INDEX,
01733 CVT_V1724_CH6_STATUS_INDEX,
01734 CVT_V1724_CH7_STATUS_INDEX,
01735 };
01736
01737 UINT32 reg_value= 0;
01738
01739
01740
01741 if( ch_index>= CVT_V1724_MAX_CHANNEL)
01742 {
01743 TRACE1( "V1724 cvt_V1724_get_channel_status bad channel '%d'!\n", ch_index);
01744 return FALSE;
01745 }
01746
01747
01748 if( !cvt_read_reg( &p_data->m_common_data, CH_STATUS[ ch_index], ®_value))
01749 {
01750 TRACE1( "V1724 CH_STATUS[%d] read failed !\n", ch_index);
01751 return FALSE;
01752 }
01753 *p_is_dac_busy= ( reg_value& CVT_V1724_CHSTS_DAC_BUSY_MSK)? TRUE: FALSE;
01754 *p_is_fifo_full= ( reg_value& CVT_V1724_CHSTS_FIFO_FULL_MSK)? TRUE: FALSE;
01755 *p_is_fifo_empty= ( reg_value& CVT_V1724_CHSTS_FIFO_EMPTY_MSK)? TRUE: FALSE;
01756 *p_is_block_remove_ok= ( reg_value& CVT_V1724_CHSTS_BLOCK_REM_OK_MSK)? TRUE: FALSE;
01757
01758 return TRUE;
01759 }
01760
01763 BOOL cvt_V1724_get_system_info( cvt_V1724_data* p_data, UINT16 *p_firmware_rev, CVT_V1724_ROM_CONFIG *p_rom_config)
01764 {
01765 UINT32 reg_value= 0;
01766
01767
01768 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_FW_REV_INDEX, ®_value))
01769 {
01770 TRACE( "V1724 CVT_V1724_FW_REV read failed !\n");
01771 return FALSE;
01772 }
01773 *p_firmware_rev= reg_value& 0x0000ffff;
01774
01775
01776
01777 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_CHKSUM_INDEX, ®_value))
01778 {
01779 TRACE( "V1724 CVT_V1724_ROM_CHKSUM_INDEX read failed !\n");
01780 return FALSE;
01781 }
01782 p_rom_config->m_chksum= reg_value& 0x000000ff;
01783
01784
01785
01786 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_CHKSUM_LEN_0_INDEX, ®_value))
01787 {
01788 TRACE( "V1724 CVT_V1724_ROM_CHKSUM_LEN_0_INDEX read failed !\n");
01789 return FALSE;
01790 }
01791 p_rom_config->m_chksum_len= reg_value& 0x000000ff;
01792 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_CHKSUM_LEN_1_INDEX, ®_value))
01793 {
01794 TRACE( "V1724 CVT_V1724_ROM_CHKSUM_LEN_1_INDEX read failed !\n");
01795 return FALSE;
01796 }
01797 p_rom_config->m_chksum_len|= (reg_value& 0x000000ff)<< 8;
01798 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_CHKSUM_LEN_2_INDEX, ®_value))
01799 {
01800 TRACE( "V1724 CVT_V1724_ROM_CHKSUM_LEN_2_INDEX read failed !\n");
01801 return FALSE;
01802 }
01803 p_rom_config->m_chksum_len|= (reg_value& 0x000000ff)<< 16;
01804
01805
01806
01807 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_CONST_0_INDEX, ®_value))
01808 {
01809 TRACE( "V1724 CVT_V1724_ROM_CONST_0_INDEX read failed !\n");
01810 return FALSE;
01811 }
01812 p_rom_config->m_const= reg_value& 0x000000ff;
01813 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_CONST_1_INDEX, ®_value))
01814 {
01815 TRACE( "V1724 CVT_V1724_ROM_CONST_1_INDEX read failed !\n");
01816 return FALSE;
01817 }
01818 p_rom_config->m_const|= (reg_value& 0x000000ff)<< 8;
01819 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_CONST_2_INDEX, ®_value))
01820 {
01821 TRACE( "V1724 CVT_V1724_ROM_CONST_2_INDEX read failed !\n");
01822 return FALSE;
01823 }
01824 p_rom_config->m_const|= (reg_value& 0x000000ff)<< 16;
01825
01826
01827
01828 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_C_CODE_INDEX, ®_value))
01829 {
01830 TRACE( "V1724 CVT_V1724_ROM_C_CODE_INDEX read failed !\n");
01831 return FALSE;
01832 }
01833 p_rom_config->m_c_code= reg_value& 0x000000ff;
01834
01835
01836
01837 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_R_CODE_INDEX, ®_value))
01838 {
01839 TRACE( "V1724 CVT_V1724_ROM_R_CODE_INDEX read failed !\n");
01840 return FALSE;
01841 }
01842 p_rom_config->m_r_code= reg_value& 0x000000ff;
01843
01844
01845
01846 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_OUI_0_INDEX, ®_value))
01847 {
01848 TRACE( "V1724 CVT_V1724_ROM_OUI_0_INDEX read failed !\n");
01849 return FALSE;
01850 }
01851 p_rom_config->m_OUI= reg_value& 0x000000ff;
01852 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_OUI_1_INDEX, ®_value))
01853 {
01854 TRACE( "V1724 CVT_V1724_ROM_OUI_1_INDEX read failed !\n");
01855 return FALSE;
01856 }
01857 p_rom_config->m_OUI|= (reg_value& 0x000000ff)<< 8;
01858 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_OUI_2_INDEX, ®_value))
01859 {
01860 TRACE( "V1724 CVT_V1724_ROM_OUI_2_INDEX read failed !\n");
01861 return FALSE;
01862 }
01863 p_rom_config->m_OUI|= (reg_value& 0x000000ff)<< 16;
01864
01865
01866
01867 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_VERSION_INDEX, ®_value))
01868 {
01869 TRACE( "V1724 CVT_V1724_ROM_VERSION_INDEX read failed !\n");
01870 return FALSE;
01871 }
01872 p_rom_config->m_version= reg_value& 0x000000ff;
01873
01874
01875
01876 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_BOARD_ID_0_INDEX, ®_value))
01877 {
01878 TRACE( "V1724 CVT_V1724_ROM_BOARD_ID_0_INDEX read failed !\n");
01879 return FALSE;
01880 }
01881 p_rom_config->m_board_id= reg_value& 0x000000ff;
01882 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_BOARD_ID_1_INDEX, ®_value))
01883 {
01884 TRACE( "V1724 CVT_V1724_ROM_BOARD_ID_1_INDEX read failed !\n");
01885 return FALSE;
01886 }
01887 p_rom_config->m_board_id|= (reg_value& 0x000000ff)<< 8;
01888 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_BOARD_ID_2_INDEX, ®_value))
01889 {
01890 TRACE( "V1724 CVT_V1724_ROM_BOARD_ID_2_INDEX read failed !\n");
01891 return FALSE;
01892 }
01893 p_rom_config->m_board_id|= (reg_value& 0x000000ff)<< 16;
01894
01895
01896
01897 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_REVISION_0_INDEX, ®_value))
01898 {
01899 TRACE( "V1724 CVT_V1724_ROM_REVISION_0_INDEX read failed !\n");
01900 return FALSE;
01901 }
01902 p_rom_config->m_revision= reg_value& 0x000000ff;
01903 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_REVISION_1_INDEX, ®_value))
01904 {
01905 TRACE( "V1724 CVT_V1724_ROM_REVISION_1_INDEX read failed !\n");
01906 return FALSE;
01907 }
01908 p_rom_config->m_revision|= (reg_value& 0x000000ff)<< 8;
01909 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_REVISION_2_INDEX, ®_value))
01910 {
01911 TRACE( "V1724 CVT_V1724_ROM_REVISION_2_INDEX read failed !\n");
01912 return FALSE;
01913 }
01914 p_rom_config->m_revision|= (reg_value& 0x000000ff)<< 16;
01915 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_REVISION_3_INDEX, ®_value))
01916 {
01917 TRACE( "V1724 CVT_V1724_ROM_REVISION_3_INDEX read failed !\n");
01918 return FALSE;
01919 }
01920 p_rom_config->m_revision|= (reg_value& 0x000000ff)<< 24;
01921
01922
01923
01924 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_SERIAL_0_INDEX, ®_value))
01925 {
01926 TRACE( "V1724 CVT_V1724_ROM_SERIAL_LSB read failed !\n");
01927 return FALSE;
01928 }
01929 p_rom_config->m_serial= reg_value& 0x00ff;
01930 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_SERIAL_1_INDEX, ®_value))
01931 {
01932 TRACE( "V1724 CVT_V1724_ROM_SERIAL_MSB read failed !\n");
01933 return FALSE;
01934 }
01935 p_rom_config->m_serial|= (reg_value& 0x00ff)<< 8;
01936
01937 return TRUE;
01938 }
01939
01941
01943 BOOL cvt_V1724_get_channel_info( cvt_V1724_data* p_data, UINT8 ch_index, UINT16 *p_firmware_rev)
01944 {
01945 static const UINT16 CH_FW_REV[ CVT_V1724_MAX_CHANNEL]=
01946 {
01947 CVT_V1724_CH0_FW_REV_INDEX,
01948 CVT_V1724_CH1_FW_REV_INDEX,
01949 CVT_V1724_CH2_FW_REV_INDEX,
01950 CVT_V1724_CH3_FW_REV_INDEX,
01951 CVT_V1724_CH4_FW_REV_INDEX,
01952 CVT_V1724_CH5_FW_REV_INDEX,
01953 CVT_V1724_CH6_FW_REV_INDEX,
01954 CVT_V1724_CH7_FW_REV_INDEX,
01955 };
01956
01957 UINT32 reg_value= 0;
01958
01959
01960
01961 if( ch_index>= CVT_V1724_MAX_CHANNEL)
01962 {
01963 TRACE1( "V1724 cvt_V1724_get_channel_info bad channel '%d'!\n", ch_index);
01964 return FALSE;
01965 }
01966
01967
01968
01969 if( !cvt_read_reg( &p_data->m_common_data, CH_FW_REV[ ch_index], ®_value))
01970 {
01971 TRACE1( "V1724 CH_FW_REV[%d] read failed !\n", ch_index);
01972 return FALSE;
01973 }
01974 *p_firmware_rev= reg_value& 0x0000ffff;
01975
01976 return TRUE;
01977 }
01978
01980
01982 BOOL cvt_V1724_set_MCST_CBLT( cvt_V1724_data* p_data, UINT8 address, MCST_CBLT_board_pos pos)
01983 {
01984 UINT32 reg_value= 0;
01985
01986
01987 CVT_V1724_SET_MCST_CBLT_ADD( reg_value, address);
01988
01989
01990 switch( pos)
01991 {
01992 case MCST_CBLT_board_pos_first:
01993 CVT_V1724_SET_MCST_CBLT_CTRL( reg_value, CVT_V1724_MCST_CBLT_CTRL_FIRST_BOARD);
01994 break;
01995 case MCST_CBLT_board_pos_mid:
01996 CVT_V1724_SET_MCST_CBLT_CTRL( reg_value, CVT_V1724_MCST_CBLT_CTRL_MID_BOARD);
01997 break;
01998 case MCST_CBLT_board_pos_last:
01999 CVT_V1724_SET_MCST_CBLT_CTRL( reg_value, CVT_V1724_MCST_CBLT_CTRL_LAST_BOARD);
02000 break;
02001 case MCST_CBLT_board_disabled:
02002 CVT_V1724_SET_MCST_CBLT_CTRL( reg_value, CVT_V1724_MCST_CBLT_CTRL_DISABLED_BOARD);
02003 break;
02004 default:
02005 TRACE1( "V1724 cvt_V1724_set_MCST_CBLT bad position indentifier '%d'!\n", pos);
02006 return FALSE;
02007 }
02008
02009 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_MCST_CBLT_ADD_CTRL_INDEX, ®_value))
02010 {
02011 TRACE( "V1724 CVT_V1724_MCST_CBLT_ADD_CTRL write failed !\n");
02012 return FALSE;
02013 }
02014
02015 return TRUE;
02016 }
02017
02019
02021 BOOL cvt_V1724_get_MCST_CBLT( cvt_V1724_data* p_data, UINT8 *p_address, MCST_CBLT_board_pos *p_pos)
02022 {
02023 UINT32 reg_value32;
02024
02025
02026 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_MCST_CBLT_ADD_CTRL_INDEX, ®_value32))
02027 {
02028 TRACE( "V1724 CVT_V1724_MCST_CBLT_ADD_CTRL read failed !\n");
02029 return FALSE;
02030 }
02031 *p_address= CVT_V1724_GET_MCST_CBLT_ADD( reg_value32);
02032
02033 switch( CVT_V1724_GET_MCST_CBLT_CTRL( reg_value32))
02034 {
02035 case CVT_V1724_MCST_CBLT_CTRL_FIRST_BOARD:
02036 *p_pos= MCST_CBLT_board_pos_first;
02037 break;
02038 case CVT_V1724_MCST_CBLT_CTRL_MID_BOARD:
02039 *p_pos= MCST_CBLT_board_pos_mid;
02040 break;
02041 case CVT_V1724_MCST_CBLT_CTRL_LAST_BOARD:
02042 *p_pos= MCST_CBLT_board_pos_last;
02043 break;
02044 case CVT_V1724_MCST_CBLT_CTRL_DISABLED_BOARD:
02045 *p_pos= MCST_CBLT_board_disabled;
02046 break;
02047 default:
02048 TRACE1( "V1724 cvt_V1724_get_MCST_CBLT bad position indentifier '%d'!\n", reg_value32);
02049 return FALSE;
02050 }
02051 return TRUE;
02052 }
02053
02055
02057 BOOL cvt_V1724_write_flash_page( cvt_V1724_data* p_data, const UINT8* page_buff, UINT32 page_index)
02058 {
02059 int i;
02060 UINT32 reg_value;
02061 UINT32 flash_addr;
02062 BOOL ret_val= TRUE;
02063
02064 flash_addr= page_index << 9;
02065
02066
02067
02068 reg_value= CVT_V1724_FLEN_EN_MSK;
02069 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1724_FLASH_EN_INDEX, ®_value))
02070 {
02071 TRACE( "V1724 CVT_V1724_FLASH_EN write failed !\n");
02072 return FALSE;
02073 }
02074
02075
02076 reg_value= CVT_V1724_FOP_PAGE_PROG_TH_BUF1;
02077 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02078 {
02079 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02080 ret_val= FALSE;
02081 goto exit_point;
02082 }
02083
02084 reg_value= (unsigned char)( flash_addr>> 16);
02085 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02086 {
02087 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02088 ret_val= FALSE;
02089 goto exit_point;
02090 }
02091 reg_value= (unsigned char)( flash_addr>> 8);
02092 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02093 {
02094 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02095 ret_val= FALSE;
02096 goto exit_point;
02097 }
02098 reg_value= (unsigned char) flash_addr;
02099 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02100 {
02101 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02102 ret_val= FALSE;
02103 goto exit_point;
02104 }
02105
02106 for (i= 0; i< V1724_FLASH_PAGE_SIZE; i++)
02107 {
02108 reg_value= page_buff[ i];
02109 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02110 {
02111 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02112 ret_val= FALSE;
02113 goto exit_point;
02114 }
02115 }
02116
02117 exit_point:
02118
02119 reg_value= CVT_V1724_FLEN_EN_MSK;
02120 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1724_FLASH_EN_INDEX, ®_value))
02121 {
02122 TRACE( "V1724 CVT_V1724_FLASH_EN write failed !\n");
02123 ret_val= FALSE;
02124 }
02125
02126
02127 cvt_delay( 50);
02128 return ret_val;
02129 }
02130
02132
02134 BOOL cvt_V1724_read_flash_page( cvt_V1724_data* p_data, UINT8* page_buff, UINT32 page_index)
02135 {
02136 int i;
02137 UINT32 reg_value;
02138 UINT32 flash_addr;
02139 BOOL ret_val= TRUE;
02140
02141 flash_addr= page_index<< 9;
02142
02143
02144 reg_value= CVT_V1724_FLEN_EN_MSK;
02145 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1724_FLASH_EN_INDEX, ®_value))
02146 {
02147 TRACE( "V1724 CVT_V1724_FLASH_EN write failed !\n");
02148 return FALSE;
02149 }
02150
02151
02152 reg_value= CVT_V1724_FOP_PAGE_READ;
02153 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02154 {
02155 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02156 ret_val= FALSE;
02157 goto exit_point;
02158 }
02159
02160 reg_value= (unsigned char)( flash_addr>> 16);
02161 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02162 {
02163 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02164 ret_val= FALSE;
02165 goto exit_point;
02166 }
02167 reg_value= (unsigned char)( flash_addr>> 8);
02168 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02169 {
02170 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02171 ret_val= FALSE;
02172 goto exit_point;
02173 }
02174 reg_value= (unsigned char) flash_addr;
02175 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02176 {
02177 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02178 ret_val= FALSE;
02179 goto exit_point;
02180 }
02181
02182
02183
02184 for( i=0; i<4; i++)
02185 {
02186 reg_value= 0;
02187 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02188 {
02189 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02190 ret_val= FALSE;
02191 goto exit_point;
02192 }
02193 }
02194
02195
02196 for (i= 0; i< V1724_FLASH_PAGE_SIZE; i++)
02197 {
02198 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02199 {
02200 TRACE( "V1724 CVT_V1724_FLASH read failed !\n");
02201 ret_val= FALSE;
02202 goto exit_point;
02203 }
02204 page_buff[ i]= ( UINT8)reg_value;
02205 }
02206
02207 exit_point:
02208
02209 reg_value= CVT_V1724_FLEN_EN_MSK;
02210 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1724_FLASH_EN_INDEX, ®_value))
02211 {
02212 TRACE( "V1724 CVT_V1724_FLASH_EN write failed !\n");
02213 ret_val= FALSE;
02214 }
02215
02216 return ret_val;
02217 }
02218
02220
02222 BOOL cvt_V1724_erase_flash_page( cvt_V1724_data* p_data, UINT32 page_index)
02223 {
02224 UINT32 reg_value;
02225 UINT32 flash_addr;
02226 BOOL ret_val= TRUE;
02227
02228 flash_addr= page_index<< 9;
02229
02230
02231 reg_value= CVT_V1724_FLEN_EN_MSK;
02232 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1724_FLASH_EN_INDEX, ®_value))
02233 {
02234 TRACE( "V1724 CVT_V1724_FLASH_EN write failed !\n");
02235 return FALSE;
02236 }
02237
02238
02239 reg_value= CVT_V1724_FOP_PAGE_ERASE;
02240 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02241 {
02242 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02243 ret_val= FALSE;
02244 goto exit_point;
02245 }
02246
02247 reg_value= (unsigned char)( flash_addr>> 16);
02248 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02249 {
02250 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02251 ret_val= FALSE;
02252 goto exit_point;
02253 }
02254 reg_value= (unsigned char)( flash_addr>> 8);
02255 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02256 {
02257 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02258 ret_val= FALSE;
02259 goto exit_point;
02260 }
02261 reg_value= (unsigned char) flash_addr;
02262 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_FLASH_DATA_INDEX, ®_value))
02263 {
02264 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02265 ret_val= FALSE;
02266 goto exit_point;
02267 }
02268 exit_point:
02269
02270 reg_value= CVT_V1724_FLEN_EN_MSK;
02271 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1724_FLASH_EN_INDEX, ®_value))
02272 {
02273 TRACE( "V1724 CVT_V1724_FLASH_EN write failed !\n");
02274 ret_val= FALSE;
02275 }
02276
02277 return ret_val;
02278 }
02279
02281
02283 BOOL cvt_V1724_fw_upgrade( cvt_V1724_data* p_data, const UINT8* data_buff, UINT32 data_size, CVT_V1724_FLASH_BANK flash_bank, BOOL (* call_back)(UINT32 written_bytes))
02284 {
02285
02286 UINT32 tot_bytes= 0;
02287 UINT8 tmp_page_w[ V1724_FLASH_PAGE_SIZE], tmp_page_r[ V1724_FLASH_PAGE_SIZE];
02288
02289 switch( flash_bank)
02290 {
02291 case CVT_V1724_FB_STANDARD:
02292 case CVT_V1724_FB_BACKUP:
02293 break;
02294 default:
02295 TRACE( "V1724 cvt_V1724_fw_upgrade Invalid flash bank!\n");
02296 return FALSE;
02297 }
02298
02299
02300 while( tot_bytes< data_size)
02301 {
02302 int i;
02303
02304 for( i= 0; ( i< V1724_FLASH_PAGE_SIZE)&& ( tot_bytes< data_size); i++)
02305 {
02306
02307 tmp_page_w[ i]= cvt_swap_bits( data_buff[ tot_bytes++]);
02308 }
02309
02310 if( !cvt_V1724_write_flash_page( p_data, tmp_page_w, flash_bank))
02311 {
02312 TRACE( "V1724 CVT_V1724_FLASH write failed !\n");
02313 return FALSE;
02314 }
02315
02316 if( !cvt_V1724_read_flash_page( p_data, tmp_page_r, flash_bank))
02317 {
02318 TRACE( "V1724 CVT_V1724_FLASH read failed !\n");
02319 return FALSE;
02320 }
02321
02322 if( memcmp( tmp_page_r, tmp_page_w, V1724_FLASH_PAGE_SIZE))
02323 {
02324
02325 TRACE( "V1724 cvt_V1724_fw_upgrade page verify failure!\n");
02326 return FALSE;
02327 }
02328 ++flash_bank;
02329 if( call_back)
02330 {
02331 if( !(*call_back)( tot_bytes))
02332 return FALSE;
02333 }
02334
02335 }
02336
02337 return TRUE;
02338 }
