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00002
00010
00011 #ifndef __CVT_V792_DEF_H
00012 #define __CVT_V792_DEF_H
00013
00015
00017 #include "cvt_common_defs.h"
00018 #include "cvt_board_commons.h"
00020
00022
00023 #define CVT_V792_THRESHOLD_NUM_A 32
00024 #define CVT_V792_THRESHOLD_NUM_N 16
00026
00027
00032
00033 #define CVT_V792_USE_DATA_QUEUE 1
00034
00036
00041
00042 #ifdef CVT_V792_USE_DATA_QUEUE
00043 #define CVT_V792_QUEUE_SIZE_DWORD (1024*1024)
00044 #endif
00045
00047
00052
00053 typedef enum
00054 {
00055 CVT_V792_TYPE_A,
00056 CVT_V792_TYPE_N,
00057 } CVT_V792_TYPES;
00058
00060
00066
00067 typedef struct
00068 {
00069 cvt_board_data m_common_data;
00070
00071
00072
00073 CVT_V792_TYPES m_type;
00074 #ifdef CVT_V792_USE_DATA_QUEUE
00075 UINT32 *m_queue;
00076 long m_queue_ini;
00077 long m_queue_end;
00078 #endif
00079
00080 } cvt_V792_data;
00081
00083
00085 #define CVT_V792_OUT_BUFFER_ADD 0x0000
00086 #define CVT_V792_FW_REV_ADD 0x1000
00087 #define CVT_V792_GEO_ADDRESS_ADD 0x1002
00088 #define CVT_V792_MCST_CBLT_ADDRESS_ADD 0x1004
00089 #define CVT_V792_BIT_SET_1_ADD 0x1006
00090 #define CVT_V792_BIT_CLEAR_1_ADD 0x1008
00091 #define CVT_V792_INT_LEVEL_ADD 0x100A
00092 #define CVT_V792_INT_VECTOR_ADD 0x100C
00093 #define CVT_V792_STATUS_1_ADD 0x100E
00094 #define CVT_V792_CONTROL_1_ADD 0x1010
00095 #define CVT_V792_ADER_HIGH_ADD 0x1012
00096 #define CVT_V792_ADER_LOW_ADD 0x1014
00097 #define CVT_V792_SINGLE_SHOT_RESET_ADD 0x1016
00098 #define CVT_V792_MCST_CBLT_CTRL_ADD 0x101A
00099 #define CVT_V792_EVENT_TRG_ADD 0x1020
00100 #define CVT_V792_STATUS_2_ADD 0x1022
00101 #define CVT_V792_EVENT_COUNTER_LOW_ADD 0x1024
00102 #define CVT_V792_EVENT_COUNTER_HIGH_ADD 0x1026
00103 #define CVT_V792_INC_EVENT_ADD 0x1028
00104 #define CVT_V792_INC_OFFSET_ADD 0x102A
00105 #define CVT_V792_LOAD_TEST_ADD 0x102C
00106 #define CVT_V792_FCLR_WND_ADD 0x102E
00107 #define CVT_V792_BIT_SET_2_ADD 0x1032
00108 #define CVT_V792_BIT_CLEAR_2_ADD 0x1034
00109 #define CVT_V792_W_MEMORY_TEST_ADDRESS_ADD 0x1036
00110 #define CVT_V792_MEMORY_TEST_WORD_HIGH_ADD 0x1038
00111 #define CVT_V792_MEMORY_TEST_WORD_LOW_ADD 0x103A
00112 #define CVT_V792_CRATE_SELECT_ADD 0x103C
00113 #define CVT_V792_TEST_EVENT_WRITE_ADD 0x103E
00114 #define CVT_V792_EVENT_COUNT_RESET_ADD 0x1040
00115 #define CVT_V792_IPED_ADD 0x1060
00116 #define CVT_V792_R_TEST_ADDRESS_ADD 0x1064
00117 #define CVT_V792_SW_COMM_ADD 0x1068
00118 #define CVT_V792_SLIDE_CONSTANT_ADD 0x106A
00119 #define CVT_V792_AAD_ADD 0x1070
00120 #define CVT_V792_BAD_ADD 0x1072
00121 #define CVT_V792_THRESHOLD_0_ADD 0x1080
00122 #define CVT_V792_THRESHOLD_1_ADD 0x1082
00123 #define CVT_V792_THRESHOLD_2_ADD 0x1084
00124 #define CVT_V792_THRESHOLD_3_ADD 0x1086
00125 #define CVT_V792_THRESHOLD_4_ADD 0x1088
00126 #define CVT_V792_THRESHOLD_5_ADD 0x108A
00127 #define CVT_V792_THRESHOLD_6_ADD 0x108C
00128 #define CVT_V792_THRESHOLD_7_ADD 0x108E
00129 #define CVT_V792_THRESHOLD_8_ADD 0x1090
00130 #define CVT_V792_THRESHOLD_9_ADD 0x1092
00131 #define CVT_V792_THRESHOLD_10_ADD 0x1094
00132 #define CVT_V792_THRESHOLD_11_ADD 0x1096
00133 #define CVT_V792_THRESHOLD_12_ADD 0x1098
00134 #define CVT_V792_THRESHOLD_13_ADD 0x109A
00135 #define CVT_V792_THRESHOLD_14_ADD 0x109C
00136 #define CVT_V792_THRESHOLD_15_ADD 0x109E
00137 #define CVT_V792_THRESHOLD_16_ADD 0x10A0
00138 #define CVT_V792_THRESHOLD_17_ADD 0x10A2
00139 #define CVT_V792_THRESHOLD_18_ADD 0x10A4
00140 #define CVT_V792_THRESHOLD_19_ADD 0x10A6
00141 #define CVT_V792_THRESHOLD_20_ADD 0x10A8
00142 #define CVT_V792_THRESHOLD_21_ADD 0x10AA
00143 #define CVT_V792_THRESHOLD_22_ADD 0x10AC
00144 #define CVT_V792_THRESHOLD_23_ADD 0x10AE
00145 #define CVT_V792_THRESHOLD_24_ADD 0x10B0
00146 #define CVT_V792_THRESHOLD_25_ADD 0x10B2
00147 #define CVT_V792_THRESHOLD_26_ADD 0x10B4
00148 #define CVT_V792_THRESHOLD_27_ADD 0x10B6
00149 #define CVT_V792_THRESHOLD_28_ADD 0x10B8
00150 #define CVT_V792_THRESHOLD_29_ADD 0x10BA
00151 #define CVT_V792_THRESHOLD_30_ADD 0x10BC
00152 #define CVT_V792_THRESHOLD_31_ADD 0x10BE
00153 #define CVT_V792_ROM_OUI_2_ADD 0x8026
00154 #define CVT_V792_ROM_OUI_1_ADD 0x802A
00155 #define CVT_V792_ROM_OUI_0_ADD 0x802E
00156 #define CVT_V792_ROM_VERSION_ADD 0x8032
00157 #define CVT_V792_ROM_BOARD_ID_2_ADD 0x8036
00158 #define CVT_V792_ROM_BOARD_ID_1_ADD 0x803A
00159 #define CVT_V792_ROM_BOARD_ID_0_ADD 0x803E
00160 #define CVT_V792_ROM_REVISION_ADD 0x804E
00161 #define CVT_V792_ROM_SERIAL_1_ADD 0x8F02
00162 #define CVT_V792_ROM_SERIAL_0_ADD 0x8F06
00164 #define CVT_V792_THRESHOLD_ADD_STEP_A 2
00165 #define CVT_V792_THRESHOLD_ADD_STEP_N 4
00167
00168 // Registers data size
00169
00170 #define CVT_V792_OUT_BUFFER_DATA_SIZE cvD64
00171 #define CVT_V792_FW_REV_DATA_SIZE cvD16
00172 #define CVT_V792_GEO_ADDRESS_DATA_SIZE cvD16
00173 #define CVT_V792_MCST_CBLT_ADDRESS_DATA_SIZE cvD16
00174 #define CVT_V792_BIT_SET_1_DATA_SIZE cvD16
00175 #define CVT_V792_BIT_CLEAR_1_DATA_SIZE cvD16
00176 #define CVT_V792_INT_LEVEL_DATA_SIZE cvD16
00177 #define CVT_V792_INT_VECTOR_DATA_SIZE cvD16
00178 #define CVT_V792_STATUS_1_DATA_SIZE cvD16
00179 #define CVT_V792_CONTROL_1_DATA_SIZE cvD16
00180 #define CVT_V792_ADER_HIGH_DATA_SIZE cvD16
00181 #define CVT_V792_ADER_LOW_DATA_SIZE cvD16
00182 #define CVT_V792_SINGLE_SHOT_RESET_DATA_SIZE cvD16
00183 #define CVT_V792_MCST_CBLT_CTRL_DATA_SIZE cvD16
00184 #define CVT_V792_EVENT_TRG_DATA_SIZE cvD16
00185 #define CVT_V792_STATUS_2_DATA_SIZE cvD16
00186 #define CVT_V792_EVENT_COUNTER_LOW_DATA_SIZE cvD16
00187 #define CVT_V792_EVENT_COUNTER_HIGH_DATA_SIZE cvD16
00188 #define CVT_V792_INC_EVENT_DATA_SIZE cvD16
00189 #define CVT_V792_INC_OFFSET_DATA_SIZE cvD16
00190 #define CVT_V792_LOAD_TEST_DATA_SIZE cvD16
00191 #define CVT_V792_FCLR_WND_DATA_SIZE cvD16
00192 #define CVT_V792_BIT_SET_2_DATA_SIZE cvD16
00193 #define CVT_V792_BIT_CLEAR_2_DATA_SIZE cvD16
00194 #define CVT_V792_W_MEMORY_TEST_ADDRESS_DATA_SIZE cvD16
00195 #define CVT_V792_MEMORY_TEST_WORD_HIGH_DATA_SIZE cvD16
00196 #define CVT_V792_MEMORY_TEST_WORD_LOW_DATA_SIZE cvD16
00197 #define CVT_V792_CRATE_SELECT_DATA_SIZE cvD16
00198 #define CVT_V792_TEST_EVENT_WRITE_DATA_SIZE cvD16
00199 #define CVT_V792_EVENT_COUNT_RESET_DATA_SIZE cvD16
00200 #define CVT_V792_IPED_DATA_SIZE cvD16
00201 #define CVT_V792_R_TEST_ADDRESS_DATA_SIZE cvD16
00202 #define CVT_V792_SW_COMM_DATA_SIZE cvD16
00203 #define CVT_V792_SLIDE_CONSTANT_DATA_SIZE cvD16
00204 #define CVT_V792_AAD_DATA_SIZE cvD16
00205 #define CVT_V792_BAD_DATA_SIZE cvD16
00206 #define CVT_V792_THRESHOLD_DATA_SIZE cvD16
00207 #define CVT_V792_ROM_OUI_2_DATA_SIZE cvD16
00208 #define CVT_V792_ROM_OUI_1_DATA_SIZE cvD16
00209 #define CVT_V792_ROM_OUI_0_DATA_SIZE cvD16
00210 #define CVT_V792_ROM_VERSION_DATA_SIZE cvD16
00211 #define CVT_V792_ROM_BOARD_ID_2_DATA_SIZE cvD16
00212 #define CVT_V792_ROM_BOARD_ID_1_DATA_SIZE cvD16
00213 #define CVT_V792_ROM_BOARD_ID_0_DATA_SIZE cvD16
00214 #define CVT_V792_ROM_REVISION_DATA_SIZE cvD16
00215 #define CVT_V792_ROM_SERIAL_1_DATA_SIZE cvD16
00216 #define CVT_V792_ROM_SERIAL_0_DATA_SIZE cvD16
00218
00219 // Registers address modifiers
00220
00221 #define CVT_V792_OUT_BUFFER_AM cvA32_S_MBLT
00222 #define CVT_V792_FW_REV_AM cvA32_S_DATA
00223 #define CVT_V792_GEO_ADDRESS_AM cvA32_S_DATA
00224 #define CVT_V792_MCST_CBLT_ADDRESS_AM cvA32_S_DATA
00225 #define CVT_V792_BIT_SET_1_AM cvA32_S_DATA
00226 #define CVT_V792_BIT_CLEAR_1_AM cvA32_S_DATA
00227 #define CVT_V792_INT_LEVEL_AM cvA32_S_DATA
00228 #define CVT_V792_INT_VECTOR_AM cvA32_S_DATA
00229 #define CVT_V792_STATUS_1_AM cvA32_S_DATA
00230 #define CVT_V792_CONTROL_1_AM cvA32_S_DATA
00231 #define CVT_V792_ADER_HIGH_AM cvA32_S_DATA
00232 #define CVT_V792_ADER_LOW_AM cvA32_S_DATA
00233 #define CVT_V792_SINGLE_SHOT_RESET_AM cvA32_S_DATA
00234 #define CVT_V792_MCST_CBLT_CTRL_AM cvA32_S_DATA
00235 #define CVT_V792_EVENT_TRG_AM cvA32_S_DATA
00236 #define CVT_V792_STATUS_2_AM cvA32_S_DATA
00237 #define CVT_V792_EVENT_COUNTER_LOW_AM cvA32_S_DATA
00238 #define CVT_V792_EVENT_COUNTER_HIGH_AM cvA32_S_DATA
00239 #define CVT_V792_INC_EVENT_AM cvA32_S_DATA
00240 #define CVT_V792_INC_OFFSET_AM cvA32_S_DATA
00241 #define CVT_V792_LOAD_TEST_AM cvA32_S_DATA
00242 #define CVT_V792_FCLR_WND_AM cvA32_S_DATA
00243 #define CVT_V792_BIT_SET_2_AM cvA32_S_DATA
00244 #define CVT_V792_BIT_CLEAR_2_AM cvA32_S_DATA
00245 #define CVT_V792_W_MEMORY_TEST_ADDRESS_AM cvA32_S_DATA
00246 #define CVT_V792_MEMORY_TEST_WORD_HIGH_AM cvA32_S_DATA
00247 #define CVT_V792_MEMORY_TEST_WORD_LOW_AM cvA32_S_DATA
00248 #define CVT_V792_CRATE_SELECT_AM cvA32_S_DATA
00249 #define CVT_V792_TEST_EVENT_WRITE_AM cvA32_S_DATA
00250 #define CVT_V792_EVENT_COUNT_RESET_AM cvA32_S_DATA
00251 #define CVT_V792_IPED_AM cvA32_S_DATA
00252 #define CVT_V792_R_TEST_ADDRESS_AM cvA32_S_DATA
00253 #define CVT_V792_SW_COMM_AM cvA32_S_DATA
00254 #define CVT_V792_SLIDE_CONSTANT_AM cvA32_S_DATA
00255 #define CVT_V792_AAD_AM cvA32_S_DATA
00256 #define CVT_V792_BAD_AM cvA32_S_DATA
00257 #define CVT_V792_THRESHOLD_AM cvA32_S_DATA
00258 #define CVT_V792_ROM_OUI_2_AM cvA32_S_DATA
00259 #define CVT_V792_ROM_OUI_1_AM cvA32_S_DATA
00260 #define CVT_V792_ROM_OUI_0_AM cvA32_S_DATA
00261 #define CVT_V792_ROM_VERSION_AM cvA32_S_DATA
00262 #define CVT_V792_ROM_BOARD_ID_2_AM cvA32_S_DATA
00263 #define CVT_V792_ROM_BOARD_ID_1_AM cvA32_S_DATA
00264 #define CVT_V792_ROM_BOARD_ID_0_AM cvA32_S_DATA
00265 #define CVT_V792_ROM_REVISION_AM cvA32_S_DATA
00266 #define CVT_V792_ROM_SERIAL_1_AM cvA32_S_DATA
00267 #define CVT_V792_ROM_SERIAL_0_AM cvA32_S_DATA
00269
00270 // Registers indexes
00271
00272
00274
00279
00280 typedef enum
00281 {
00282 CVT_V792_OUT_BUFFER_INDEX,
00283 CVT_V792_FW_REV_INDEX,
00284 CVT_V792_GEO_ADDRESS_INDEX,
00285 CVT_V792_MCST_CBLT_ADDRESS_INDEX,
00286 CVT_V792_BIT_SET_1_INDEX,
00287 CVT_V792_BIT_CLEAR_1_INDEX,
00288 CVT_V792_INT_LEVEL_INDEX,
00289 CVT_V792_INT_VECTOR_INDEX,
00290 CVT_V792_STATUS_1_INDEX,
00291 CVT_V792_CONTROL_1_INDEX,
00292 CVT_V792_ADER_HIGH_INDEX,
00293 CVT_V792_ADER_LOW_INDEX,
00294 CVT_V792_SINGLE_SHOT_RESET_INDEX,
00295 CVT_V792_MCST_CBLT_CTRL_INDEX,
00296 CVT_V792_EVENT_TRG_INDEX,
00297 CVT_V792_STATUS_2_INDEX,
00298 CVT_V792_EVENT_COUNTER_LOW_INDEX,
00299 CVT_V792_EVENT_COUNTER_HIGH_INDEX,
00300 CVT_V792_INC_EVENT_INDEX,
00301 CVT_V792_INC_OFFSET_INDEX,
00302 CVT_V792_LOAD_TEST_INDEX,
00303 CVT_V792_FCLR_WND_INDEX,
00304 CVT_V792_BIT_SET_2_INDEX,
00305 CVT_V792_BIT_CLEAR_2_INDEX,
00306 CVT_V792_W_MEMORY_TEST_ADDRESS_INDEX,
00307 CVT_V792_MEMORY_TEST_WORD_HIGH_INDEX,
00308 CVT_V792_MEMORY_TEST_WORD_LOW_INDEX,
00309 CVT_V792_CRATE_SELECT_INDEX,
00310 CVT_V792_TEST_EVENT_WRITE_INDEX,
00311 CVT_V792_EVENT_COUNT_RESET_INDEX,
00312 CVT_V792_IPED_INDEX,
00313 CVT_V792_R_TEST_ADDRESS_INDEX,
00314 CVT_V792_SW_COMM_INDEX,
00315 CVT_V792_SLIDE_CONSTANT_INDEX,
00316 CVT_V792_AAD_INDEX,
00317 CVT_V792_BAD_INDEX,
00318 CVT_V792_THRESHOLD_0_INDEX,
00319 CVT_V792_THRESHOLD_1_INDEX,
00320 CVT_V792_THRESHOLD_2_INDEX,
00321 CVT_V792_THRESHOLD_3_INDEX,
00322 CVT_V792_THRESHOLD_4_INDEX,
00323 CVT_V792_THRESHOLD_5_INDEX,
00324 CVT_V792_THRESHOLD_6_INDEX,
00325 CVT_V792_THRESHOLD_7_INDEX,
00326 CVT_V792_THRESHOLD_8_INDEX,
00327 CVT_V792_THRESHOLD_9_INDEX,
00328 CVT_V792_THRESHOLD_10_INDEX,
00329 CVT_V792_THRESHOLD_11_INDEX,
00330 CVT_V792_THRESHOLD_12_INDEX,
00331 CVT_V792_THRESHOLD_13_INDEX,
00332 CVT_V792_THRESHOLD_14_INDEX,
00333 CVT_V792_THRESHOLD_15_INDEX,
00334 CVT_V792_THRESHOLD_16_INDEX,
00335 CVT_V792_THRESHOLD_17_INDEX,
00336 CVT_V792_THRESHOLD_18_INDEX,
00337 CVT_V792_THRESHOLD_19_INDEX,
00338 CVT_V792_THRESHOLD_20_INDEX,
00339 CVT_V792_THRESHOLD_21_INDEX,
00340 CVT_V792_THRESHOLD_22_INDEX,
00341 CVT_V792_THRESHOLD_23_INDEX,
00342 CVT_V792_THRESHOLD_24_INDEX,
00343 CVT_V792_THRESHOLD_25_INDEX,
00344 CVT_V792_THRESHOLD_26_INDEX,
00345 CVT_V792_THRESHOLD_27_INDEX,
00346 CVT_V792_THRESHOLD_28_INDEX,
00347 CVT_V792_THRESHOLD_29_INDEX,
00348 CVT_V792_THRESHOLD_30_INDEX,
00349 CVT_V792_THRESHOLD_31_INDEX,
00350 CVT_V792_ROM_OUI_2_INDEX,
00351 CVT_V792_ROM_OUI_1_INDEX,
00352 CVT_V792_ROM_OUI_0_INDEX,
00353 CVT_V792_ROM_VERSION_INDEX,
00354 CVT_V792_ROM_BOARD_ID_2_INDEX,
00355 CVT_V792_ROM_BOARD_ID_1_INDEX,
00356 CVT_V792_ROM_BOARD_ID_0_INDEX,
00357 CVT_V792_ROM_REVISION_INDEX,
00358 CVT_V792_ROM_SERIAL_1_INDEX,
00359 CVT_V792_ROM_SERIAL_0_INDEX,
00360 } CVT_V792_REG_INDEX;
00361
00363
00366
00367 typedef enum
00368 {
00369 CVT_V792_THRESHOLD_ALL= -1,
00370 CVT_V792_THRESHOLD_0= 0,
00371 CVT_V792_THRESHOLD_1,
00372 CVT_V792_THRESHOLD_2,
00373 CVT_V792_THRESHOLD_3,
00374 CVT_V792_THRESHOLD_4,
00375 CVT_V792_THRESHOLD_5,
00376 CVT_V792_THRESHOLD_6,
00377 CVT_V792_THRESHOLD_7,
00378 CVT_V792_THRESHOLD_8,
00379 CVT_V792_THRESHOLD_9,
00380 CVT_V792_THRESHOLD_10,
00381 CVT_V792_THRESHOLD_11,
00382 CVT_V792_THRESHOLD_12,
00383 CVT_V792_THRESHOLD_13,
00384 CVT_V792_THRESHOLD_14,
00385 CVT_V792_THRESHOLD_15,
00386 CVT_V792_THRESHOLD_16,
00387 CVT_V792_THRESHOLD_17,
00388 CVT_V792_THRESHOLD_18,
00389 CVT_V792_THRESHOLD_19,
00390 CVT_V792_THRESHOLD_20,
00391 CVT_V792_THRESHOLD_21,
00392 CVT_V792_THRESHOLD_22,
00393 CVT_V792_THRESHOLD_23,
00394 CVT_V792_THRESHOLD_24,
00395 CVT_V792_THRESHOLD_25,
00396 CVT_V792_THRESHOLD_26,
00397 CVT_V792_THRESHOLD_27,
00398 CVT_V792_THRESHOLD_28,
00399 CVT_V792_THRESHOLD_29,
00400 CVT_V792_THRESHOLD_30,
00401 CVT_V792_THRESHOLD_31,
00402 } cvt_V792_threshold_id;
00403
00404 #define CVT_V792_MAX_THRESHOLD_A 32
00405 #define CVT_V792_MAX_THRESHOLD_N 16
00407
00408
00411
00412 typedef enum
00413 {
00414 CVT_V792_THRESHOLD_VALUE_MSK = 0x00FF,
00415 CVT_V792_THRESHOLD_KILL_MSK = 0x0100,
00416 } CVT_V792_THRESHOLD_MSK;
00417
00419
00423
00424 typedef enum
00425 {
00426 CVT_V792_BSC1_BERR_FLAG_MSK = 0x0008,
00427 CVT_V792_BSC1_SEL_ADDR_MSK = 0x0010,
00428 CVT_V792_BSC1_SOFT_RESET_MSK = 0x0080,
00429 } CVT_V792_BIT_SET_CLEAR_1_MSK;
00430
00432
00436
00437 typedef enum
00438 {
00439 CVT_V792_STS1_DREADY_MSK = 0x0001,
00440 CVT_V792_STS1_GLOBAL_DREADY_MSK = 0x0002,
00441 CVT_V792_STS1_BUSY_MSK = 0x0004,
00442 CVT_V792_STS1_GLOBAL_BUSY_MSK = 0x0008,
00443 CVT_V792_STS1_AMNESIA_MSK = 0x0010,
00444 CVT_V792_STS1_PURGED_MSK = 0x0020,
00445 CVT_V792_STS1_TERM_ON_MSK = 0x0040,
00446 CVT_V792_STS1_TERM_OFF_MSK = 0x0080,
00447 CVT_V792_STS1_EVREADY_MSK = 0x0100,
00451 } CVT_V792_STATUS_1_MSK;
00452
00454
00458
00459 typedef enum
00460 {
00461 CVT_V792_CTRL1_BLKEND_MSK = 0x0004,
00462 CVT_V792_CTRL1_PROG_RESET_MSK = 0x0010,
00463 CVT_V792_CTRL1_BERR_ENABLE_MSK = 0x0020,
00464 CVT_V792_CTRL1_ALIGN64_MSK = 0x0040,
00465 } CVT_V792_CONTROL_1_MSK;
00466
00468
00472
00473 typedef enum
00474 {
00475 CVT_V792_MCCTRL_DISABLED_BOARD_MSK = 0x0000,
00476 CVT_V792_MCCTRL_LAST_BOARD_MSK = 0x0001,
00477 CVT_V792_MCCTRL_FIRST_BOARD_MSK = 0x0002,
00478 CVT_V792_MCCTRL_MID_BOARD_MSK = 0x0003,
00479 } CVT_V792_MCST_CBLT_CTRL_MSK;
00480
00482
00486
00487 typedef enum
00488 {
00489 CVT_V792_STS2_BUFFER_EMPTY_MSK = 0x0002,
00490 CVT_V792_STS2_BUFFER_FULL_MSK = 0x0004,
00491 CVT_V792_STS2_DSEL_0_MSK = 0x0010,
00492 CVT_V792_STS2_DSEL_1_MSK = 0x0020,
00493 CVT_V792_STS2_CSEL_0_MSK = 0x0040,
00494 CVT_V792_STS2_CSEL_1_MSK = 0x0080,
00495 } CVT_V792_STATUS_2_MSK;
00496
00497 #define CVT_V792_STS2_PIGGY_BACK_TYPE_MSK 0x00F0
00498 #define CVT_V792_GET_PIGGY_BACK_TYPE( reg) ((((UINT16)reg)& CVT_V792_STS2_PIGGY_BACK_TYPE_MSK)>> 4)
00499 #define CVT_V792_SET_PIGGY_BACK_TYPE( reg) reg= (((UINT16)reg)& ~CVT_V792_STS2_PIGGY_BACK_TYPE_MSK)| ((((UINT16)value)<< 4)&CVT_V792_STS2_PIGGY_BACK_TYPE_MSK)
00501
00502
00505
00506 typedef enum
00507 {
00508 CVT_V792_BSC2_TEST_MEM_MSK = 0x0001,
00509 CVT_V792_BSC2_OFFLINE_MSK = 0x0002,
00510 CVT_V792_BSC2_CLEAR_DATA_MSK = 0x0004,
00511 CVT_V792_BSC2_OVER_RANGE_DIS_MSK= 0x0008,
00512 CVT_V792_BSC2_LOW_THR_DIS_MSK = 0x0010,
00513 CVT_V792_BSC2_TEST_ACQ_MSK = 0x0040,
00514 CVT_V792_BSC2_SLIDE_EN_MSK = 0x0080,
00515 CVT_V792_BSC2_STEP_TH_MSK = 0x0100,
00516 CVT_V792_BSC2_AUTO_INC_MSK = 0x0800,
00517 CVT_V792_BSC2_EMPTY_EN_MSK = 0x1000,
00518 CVT_V792_BSC2_SLIDE_SUB_EN_MSK = 0x2000,
00519 CVT_V792_BSC2_ALL_TRG_MSK = 0x4000,
00520 } CVT_V792_BIT_SET_CLEAR_2_MSK;
00521
00523
00525
00527
00529
00531
00532
00533
00535
00537
00549
00550 BOOL cvt_V792_open( cvt_V792_data* p_data, UINT16 base_address, long vme_handle, CVT_V792_TYPES type);
00551
00553
00561
00562 BOOL cvt_V792_close( cvt_V792_data* p_data);
00563
00565
00566
00567
00569
00570
00572
00573
00574
00576
00578
00586
00587 BOOL cvt_V792_set_geo_address( cvt_V792_data* p_data, UINT8 value);
00588
00590
00598
00599 BOOL cvt_V792_get_geo_address( cvt_V792_data* p_data, UINT8 *p_value);
00600
00602
00611
00612 BOOL cvt_V792_set_MCST_CBLT_address( cvt_V792_data* p_data, UINT8 value);
00613
00615
00624
00625 BOOL cvt_V792_get_MCST_CBLT_address( cvt_V792_data* p_data, UINT8 *p_value);
00626
00628
00636
00637 BOOL cvt_V792_set_bit_set_1( cvt_V792_data* p_data, UINT16 value);
00638
00640
00648
00649 BOOL cvt_V792_set_bit_clear_1( cvt_V792_data* p_data, UINT16 value);
00650
00652
00660
00661 BOOL cvt_V792_set_interrupt_level( cvt_V792_data* p_data, UINT8 value);
00662
00664
00672
00673 BOOL cvt_V792_get_interrupt_level( cvt_V792_data* p_data, UINT8 *p_value);
00674
00676
00684
00685 BOOL cvt_V792_set_interrupt_vector( cvt_V792_data* p_data, UINT8 value);
00686
00688
00696
00697 BOOL cvt_V792_get_interrupt_vector( cvt_V792_data* p_data, UINT8 *p_value);
00698
00700
00708
00709 BOOL cvt_V792_get_status_1( cvt_V792_data* p_data, UINT16 *p_value);
00710
00712
00721
00722 BOOL cvt_V792_set_control_1( cvt_V792_data* p_data, UINT16 value);
00723
00725
00733
00734 BOOL cvt_V792_get_control_1( cvt_V792_data* p_data, UINT16 *p_value);
00735
00737
00746
00747 BOOL cvt_V792_clear_bitmask_control_1( cvt_V792_data* p_data, CVT_V792_CONTROL_1_MSK value);
00748
00750
00759
00760 BOOL cvt_V792_set_bitmask_control_1( cvt_V792_data* p_data, CVT_V792_CONTROL_1_MSK value);
00761
00763
00772
00773 BOOL cvt_V792_clear_bitmask_control_1( cvt_V792_data* p_data, CVT_V792_CONTROL_1_MSK value);
00774
00776
00784
00785 BOOL cvt_V792_set_ader_high( cvt_V792_data* p_data, UINT8 value);
00786
00788
00796
00797 BOOL cvt_V792_get_ader_high( cvt_V792_data* p_data, UINT8 *p_value);
00798
00800
00808
00809 BOOL cvt_V792_set_ader_high( cvt_V792_data* p_data, UINT8 value);
00810
00812
00820
00821 BOOL cvt_V792_get_ader_low( cvt_V792_data* p_data, UINT8 *p_value);
00822
00824
00834
00835 BOOL cvt_V792_single_shot_reset( cvt_V792_data* p_data);
00836
00838
00846
00847 BOOL cvt_V792_set_MCST_CBLT_control( cvt_V792_data* p_data, UINT8 value);
00848
00850
00858
00859 BOOL cvt_V792_get_MCST_CBLT_control( cvt_V792_data* p_data, UINT8 *p_value);
00860
00862
00870
00871 BOOL cvt_V792_set_event_trigger( cvt_V792_data* p_data, UINT8 value);
00872
00874
00882
00883 BOOL cvt_V792_get_event_trigger( cvt_V792_data* p_data, UINT8 *p_value);
00884
00886
00894
00895 BOOL cvt_V792_get_status_2( cvt_V792_data* p_data, UINT16 *p_value);
00896
00898
00909
00910 BOOL cvt_V792_set_threshold( cvt_V792_data* p_data, cvt_V792_threshold_id threshold_id, UINT16 value);
00911
00913
00921
00922 BOOL cvt_V792_set_bit_set_2( cvt_V792_data* p_data, UINT16 value);
00923
00925
00933
00934 BOOL cvt_V792_set_bit_clear_2( cvt_V792_data* p_data, UINT16 value);
00935
00937
00938
00939
00941
00943
00952
00953 BOOL cvt_V792_set_sliding_scale( cvt_V792_data* p_data, BOOL enable, UINT8 sliding_constant);
00954
00956
00967
00968 BOOL cvt_V792_set_zero_suppression( cvt_V792_data* p_data, BOOL enable, BOOL step_threshold, const UINT16* thresholds_buff);
00969
00971
00979
00980 BOOL cvt_V792_set_overflow_suppression( cvt_V792_data* p_data, BOOL enable);
00981
00983
00992
00993 BOOL cvt_V792_set_MEB( cvt_V792_data* p_data, BOOL empty_enable, BOOL auto_incr_enable);
00994
00996
01005
01006 BOOL cvt_V792_set_event_counter( cvt_V792_data* p_data, BOOL count_all_events, BOOL reset_count);
01007
01009
01020
01021 BOOL cvt_V792_read_MEB( cvt_V792_data* p_data, void* p_buff, UINT32* p_buff_size);
01022
01024
01032
01033 BOOL cvt_V792_set_fast_clear_window( cvt_V792_data* p_data, UINT16 value);
01034
01036
01048
01049 BOOL cvt_V792_set_acquisition_mode( cvt_V792_data* p_data, BOOL sliding_scale_enable, BOOL zero_suppression_enable, BOOL overflow_suppression_enable, BOOL empty_enable, BOOL count_all_events);
01050
01052
01062
01063 BOOL cvt_V792_set_interrupt( cvt_V792_data* p_data, UINT8 level, UINT8 vector, UINT8 event_number);
01064
01066
01077
01078 BOOL cvt_V792_set_readout_mode( cvt_V792_data* p_data, BOOL bus_error_enable, BOOL block_end_enable, BOOL align64_enable);
01079
01081
01091
01092 BOOL cvt_V792_get_status( cvt_V792_data* p_data, BOOL *p_is_data_ready, BOOL *p_is_busy, BOOL *p_is_term_on, BOOL *p_is_buffer_full);
01093
01095
01105
01106 BOOL cvt_V792_set_thresholds( cvt_V792_data* p_data, BOOL step_threshold, const UINT8* thresholds_value_buff);
01107
01109
01118
01119 BOOL cvt_V792_set_channel_enable( cvt_V792_data* p_data, UINT32 enable_msk);
01120
01122
01129
01130 BOOL cvt_V792_set_crate_number( cvt_V792_data* p_data, UINT8 crate_number);
01131
01133
01141
01142 BOOL cvt_V792_set_pedestal( cvt_V792_data* p_data, UINT8 value);
01143
01145
01153
01154 BOOL cvt_V792_get_event_counter( cvt_V792_data* p_data, UINT32* p_counter);
01155
01157
01167
01168 BOOL cvt_V792_get_system_info( cvt_V792_data* p_data, UINT16 *p_firmware_rev, UINT8 *p_piggy_back_type, UINT16 *p_serial_number);
01169
01171
01178
01179 BOOL cvt_V792_software_reset( cvt_V792_data* p_data);
01180
01182
01190
01191 BOOL cvt_V792_data_clear( cvt_V792_data* p_data);
01192
01193 #ifdef CVT_V792_USE_DATA_QUEUE
01194
01196
01211
01212 BOOL cvt_V792_peek_event( cvt_V792_data *p_data, UINT32 *out_buff, long *p_out_buff_size, UINT32 *p_event_count);
01213
01215
01225
01226 BOOL cvt_V792_inqueue( cvt_V792_data* p_data, const UINT32* in_buff, UINT32 in_buff_size);
01227
01229
01239
01240 BOOL cvt_V792_dequeue( cvt_V792_data* p_data, UINT32 *out_buff, UINT32 out_buff_size);
01241
01243
01249
01250 long cvt_V792_get_queue_free( cvt_V792_data* p_data);
01251
01253
01259
01260 long cvt_V792_get_queue_length( cvt_V792_data* p_data);
01261
01262 #endif // CVT_V792_USE_DATA_QUEUE
01263
01265
01275
01276 BOOL cvt_V792_set_MCST_CBLT( cvt_V792_data* p_data, UINT8 address, MCST_CBLT_board_pos pos);
01277
01278 #endif // __CVT_V792_DEF_H
